公开(公告)号：US11569179B2

公开(公告)日：2023-01-31

申请号：US16953255

申请日：2020-11-19

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L21/56 ,  H01L21/48

Abstract: A semiconductor package structure and a method for manufacturing a semiconductor package structure are provided. The package structure includes an outer lead portion, an inner lead portion, an encapsulant, and a first conductive layer. The outer lead portion has a first surface and a second surface opposite to the first surface. The inner lead portion is connected to the outer lead portion. The inner lead portion has a first surface and a second surface opposite to the first surface. The encapsulant covers the first surface of the outer lead portion and the first surface of the inner lead portion. The second surface of the outer lead portion and the second surface of the inner lead portion are substantially coplanar and are recessed from a surface of the encapsulant. The first conductive layer is disposed on the second surface of the outer lead portion.

公开(公告)号：US10049893B2

公开(公告)日：2018-08-14

申请号：US15453656

申请日：2017-03-08

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee ,  Yu-Tzu Peng

IPC: H01L23/48 ,  H01L21/44 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/10

Abstract: A semiconductor package comprises a substrate, a pad, a first isolation layer, an interconnection layer, and a conductive post. The substrate has a first surface and a second surface opposite the first surface. The pad has a first portion and a second portion on the first surface of the substrate. The first isolation layer is disposed on the first surface and covers the first portion of the pad, and the first isolation layer has a top surface. The interconnection layer is disposed on the second portion of the pad and has a top surface. The conductive post is disposed on the top surface of the first isolation layer and on the top surface of the interconnection layer. The top surface of the first isolation layer and the top surface of the interconnection layer are substantially coplanar.

公开(公告)号：US10002843B2

公开(公告)日：2018-06-19

申请号：US14667317

申请日：2015-03-24

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Kuang-Hsiung Chen ,  Sheng-Ming Wang ,  Yu-Ying Lee

IPC: H01L23/48 ,  H01L23/498 ,  H01L23/52 ,  H01L23/31 ,  H05K3/20 ,  H01L23/00 ,  H05K1/11 ,  H05K3/10

CPC classification number: H01L24/17 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3157 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/49 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/16258 ,  H01L2224/17106 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48101 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48245 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/0665 ,  H01L2924/1511 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/10 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: The present disclosure relates to a semiconductor substrate structure, semiconductor package and method of manufacturing the same. The semiconductor substrate structure includes a conductive structure and a dielectric structure. The conductive structure has a first conductive surface and a second conductive surface opposite to the first conductive surface. The dielectric structure covers at least a portion of the conductive structure, and has a first dielectric surface and a second dielectric surface opposite to the first dielectric surface. The first conductive surface does not protrude from the first dielectric surface, and the second conductive surface is recessed from the second dielectric surface. The dielectric structure includes, or is formed from, a photo-sensitive resin, and the dielectric structure defines a dielectric opening in the second dielectric surface to expose a portion of the second conductive surface.

公开(公告)号：US09984989B2

公开(公告)日：2018-05-29

申请号：US14855849

申请日：2015-09-16

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/49 ,  H01L23/00 ,  H01L23/31 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L21/4853 ,  H01L23/3114 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/13 ,  H01L2224/13012 ,  H01L2224/13025 ,  H01L2224/1412 ,  H01L2224/73204 ,  H01L2924/15313 ,  H01L2924/3512

Abstract: A semiconductor substrate includes an insulating layer, a first conductive patterned layer disposed adjacent to a first surface of the insulating layer, and conductive bumps disposed on the first conductive patterned layer. Each conductive bump has a first dimension along a first direction and a second dimension along a second direction perpendicular to the first direction, and the first dimension is greater than the second dimension. A semiconductor package structure includes the semiconductor substrate, at least one die electrically connected to the conductive bumps, and a molding compound encapsulating the conductive bumps.

公开(公告)号：US09911702B2

公开(公告)日：2018-03-06

申请号：US14268981

申请日：2014-05-02

Applicant: Advanced Semiconductor Engineering, Inc.

Inventor： Tien-Szu Chen ,  Sheng-Ming Wang ,  Kuang-Hsiung Chen ,  Yu-Ying Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/37001 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package structure and a fabrication method thereof are provided. The fabrication method comprises: providing a substrate strip, the substrate strip comprising a plurality of substrate units; disposing a plurality of chips on the plurality of substrate units; disposing a packaging encapsulant on the substrate strip to encapsulate the chips; forming a warp-resistant layer on a top surface of the packaging encapsulant; and dividing the substrate strip to separate the plurality of substrate units to further fabricate a plurality of semiconductor package structures, wherein the warp-resistant layer is formed of a selected material with a selected thickness to make a variation of warpage of the semiconductor package structure at a temperature between 25° C. and 260° C. to be smaller than 560 μm.