公开(公告)号：US20060231841A1

公开(公告)日：2006-10-19

申请号：US11396715

申请日：2006-04-04

申请人： Eiichi Okuno ,  Toshio Sakakibara

发明人： Eiichi Okuno ,  Toshio Sakakibara

IPC分类号： H01L29/76

CPC分类号： H01L27/088 ,  H01L21/823487 ,  H01L29/66068

摘要： A silicon carbide semiconductor device includes a semiconductor element disposed in a semiconductor substrate having a first conductive type silicon carbide layer and a silicon substrate. The device includes: a trench on the silicon carbide layer to reach the silicon substrate; and a conductive layer in the trench between the silicon carbide layer and the silicon substrate to connect to both of them. The semiconductor element is a vertical type semiconductor element so that current flows on both of a top surface portion and a backside surface portion of the semiconductor substrate. The current flows through the conductive layer.

摘要翻译： 碳化硅半导体器件包括设置在具有第一导电型碳化硅层和硅衬底的半导体衬底中的半导体元件。 该器件包括：在碳化硅层上的沟槽以到达硅衬底; 以及在碳化硅层和硅衬底之间的沟槽中的导电层以连接到它们两者。 半导体元件是垂直型半导体元件，使得电流在半导体衬底的顶表面部分和后表面部分两者上流动。 电流流过导电层。

公开(公告)号：US06525375B1

公开(公告)日：2003-02-25

申请号：US09688154

申请日：2000-10-16

申请人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

发明人： Hitoshi Yamaguchi ,  Toshio Sakakibara ,  Jun Sakakibara ,  Takumi Shibata ,  Toshiyuki Morishita

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66378 ,  H01L29/66659 ,  H01L29/66704 ,  H01L29/66734 ,  H01L29/66787 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/749 ,  H01L29/78 ,  H01L29/7803 ,  H01L29/7809 ,  H01L29/7816 ,  H01L29/7817 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/7828 ,  H01L29/7835

摘要： In a semiconductor device, a p-type base region is provided in an n−-type substrate to extend from a principal surface of the substrate in a perpendicular direction to the principal surface. An n+-type source region extends in the p-type base region from the principal surface in the perpendicular direction, and an n+-type drain region extends in the substrate separately from the p-type base region with a drift region interposed therebetween. A trench is formed to penetrate the p-type base region from the n+-type source region in a direction parallel to the principal surface. A gate electrode is formed in the trench through a gate insulating film. Accordingly, a channel region can be formed with a channel width in a depth direction of the trench when a voltage is applied to the gate electrode.

摘要翻译： 在半导体器件中，p型基极区域设置在n型衬底中，以从垂直于主表面的方向从衬底的主表面延伸。 n +型源极区域在垂直方向上从主表面延伸到p型基极区域中，并且n +型漏极区域在p型基极区域中与P型基极区域分开延伸，并且其间插入漂移区域。 形成沟槽，以在平行于主表面的方向上从n +型源极区域穿透p型基极区域。 栅电极通过栅极绝缘膜形成在沟槽中。 因此，当向栅电极施加电压时，可以在沟槽的深度方向上形成沟道区域。

公开(公告)号：US5072277A

公开(公告)日：1991-12-10

申请号：US549299

申请日：1990-07-09

申请人： Toshio Sakakibara ,  Masami Yamaoka

发明人： Toshio Sakakibara ,  Masami Yamaoka

IPC分类号： H01L21/18 ,  H01L21/20 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/08 ,  H01L27/088 ,  H01L27/092 ,  H01L29/786

CPC分类号： H01L21/76297 ,  H01L21/187 ,  H01L21/2007 ,  H01L21/76251 ,  H01L21/8234 ,  H01L27/0688 ,  H01L27/088

摘要： A semiconductor device is provided which comprises a single crystalline substrate having a main surface, an insulating layer formed on the main surface of the single crystalline substrate, and a semiconductor region of a single crystal formed on the insulating layer, wherein the semiconductor region has top and bottom surfaces and a thickness of not more than 6 .mu.m and an impurity is doped in the semiconductor region from the top to bottom surfaces thereof, a concentration of the impurity gradually decreasing from the top to bottom surfaces, whereby the semiconductor region is made a first conductivity type by the doped impurity. The semiconductor device further comprises an insulating gate type field effect transistor including source and drain regions in the semiconductor region, the source and drain regions having a conductive type opposite to that of the first conductivity type, and further there is provided a process for manufacturing such a semiconductor device.

摘要翻译： 提供一种半导体器件，其包括具有主表面的单晶衬底，形成在单晶衬底的主表面上的绝缘层和形成在绝缘层上的单晶体的半导体区域，其中半导体区域具有顶部 和底面，厚度不大于6μm，杂质从上到下掺杂在半导体区域中，杂质浓度从顶部向下表面逐渐减小，由此制成半导体区域 通过掺杂杂质的第一导电类型。 半导体器件还包括在半导体区域中包括源极和漏极区域的绝缘栅极型场效应晶体管，源极和漏极区域具有与第一导电类型相反的导电类型，并且还提供了一种用于制造这样的 半导体器件。

公开(公告)号：US07663181B2

公开(公告)日：2010-02-16

申请号：US11206271

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura

IPC分类号： H01L29/72

CPC分类号： H01L21/823487 ,  H01L29/7722

摘要： A semiconductor device includes a vertical field-effect transistor having a substrate of first conduction type in a substrate base, a drain electrode formed on a first surface of the substrate, an epitaxial layer of first conduction type formed on a second surface of the substrate, a source region of first conduction type formed on the semiconductor base, a source ohmic contact metal film in ohmic contact with the source region, trenches formed from the second surface of the semiconductor base, and a gate region of second conduction type formed along the trenches. The semiconductor device further includes a gate rise metal film in ohmic contact with the draw-out layer of the gate region on the bottom of the trenches and rising to the second surface of the semiconductor base, and a gate draw-out metal film connected to the gate rise metal film from the second surface of the semiconductor base.

摘要翻译： 半导体器件包括：垂直场效应晶体管，其具有在基板基底中的第一导电类型的衬底;形成在衬底的第一表面上的漏电极，形成在衬底的第二表面上的第一导电类型的外延层; 在半导体基底上形成的第一导电类型的源极区域，与源极区欧姆接触的源欧姆接触金属膜，从半导体基底的第二表面形成的沟槽和沿着沟槽形成的第二导电类型的栅极区域 。 半导体器件还包括与沟槽底部的栅极区域的引出层欧姆接触并上升到半导体基底的第二表面的栅极上升金属膜，以及连接到 来自半导体基底的第二表面的栅极上升金属膜。

公开(公告)号：US20060076613A1

公开(公告)日：2006-04-13

申请号：US11206212

申请日：2005-08-18

申请人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

发明人： Takasumi Ohyanagi ,  Atsuo Watanabe ,  Toshio Sakakibara ,  Tsuyoshi Yamamoto ,  Hiroki Nakamura ,  Rajesh Malhan

IPC分类号： H01L29/94

CPC分类号： H01L29/1066 ,  H01L29/7722 ,  H01L29/8083

摘要： A semiconductor device includes (a) a vertical field effect transistor, the vertical field effect transistor including a drain electrode formed on a first surface of a first conductivity type of a semiconductor, a pair of first trenches formed from a second surface of the semiconductor, control regions of a second conductivity type formed respectively along the first trenches, a source region of the first conductivity type formed along the second surface of the semiconductor between the first trenches, a source electrode joined to the source region, and a gate electrode adjacent to the control regions, (b) a pair of second trenches formed from the second surface of the semiconductor independently of the field effect transistor, (c) control regions of the second conductivity type formed along the second trenches, and (d) a diode having a junction formed on the second surface between the second trenches.

摘要翻译： 半导体器件包括（a）垂直场效应晶体管，垂直场效应晶体管包括形成在第一导电类型的半导体的第一表面上的漏电极，由半导体的第二表面形成的一对第一沟槽， 沿着第一沟槽分别形成的第二导电类型的控制区域，沿着第一沟槽之间的半导体的第二表面形成的第一导电类型的源极区域，与源极区域连接的源极电极和与源极区域相邻的栅电极 控制区域，（b）与场效应晶体管独立地由半导体的第二表面形成的一对第二沟槽，（c）沿着第二沟槽形成的第二导电类型的控制区，以及（d）二极管， 在第二沟槽之间的第二表面上形成的结。

公开(公告)号：US06831331B2

公开(公告)日：2004-12-14

申请号：US09945621

申请日：2001-09-05

申请人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

发明人： Yasuhiro Kitamura ,  Toshio Sakakibara ,  Kenji Kohno ,  Shoji Mizuno ,  Yoshiaki Nakayama ,  Hiroshi Maeda ,  Makio Iida ,  Hiroshi Fujimoto ,  Mitsuhiro Saitou ,  Hiroshi Imai ,  Hiroyuki Ban

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L21/8249 ,  H01L27/0251 ,  H01L27/0623 ,  H01L27/085 ,  H01L29/1087 ,  H01L29/66674 ,  H01L29/7395 ,  H01L29/7801 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor device is provided having a power transistor structure. The power transistor structure includes a plurality of first wells disposed independently at a surface portion of a semiconductor layer; a deep region having a portion disposed in the semiconductor layer between the first wells; a drain electrode connected to respective drain regions in the first wells; a source electrode connected to respective source regions and channel well regions in the first wells, such that either the drain electrode or the source electrode is connected to an inductive load; and a connecting member for supplying the deep region with a source potential, where the connecting member is configurable to connect to the drain electrode when the drain electrode is connected to the inductive load and to connect to the source electrode when the source electrode is connected to said inductive load.

摘要翻译： 提供具有功率晶体管结构的半导体器件。 功率晶体管结构包括独立地设置在半导体层的表面部分处的多个第一阱; 深部区域，其具有设置在所述第一阱之间的所述半导体层中的部分; 漏电极，连接到所述第一阱中的相应的漏极区; 源电极，其连接到第一阱中的各个源极区域和沟道阱区域，使得漏极电极或源极电极连接到感性负载; 以及连接构件，用于向深区域提供源极电位，其中当漏电极连接到感性负载时，连接构件可配置为连接到漏电极，并且当源电极连接到源电极时连接到源电极 表示感性负载。

公开(公告)号：US6104078A

公开(公告)日：2000-08-15

申请号：US941756

申请日：1997-09-30

申请人： Makio Iida ,  Mitsuhiro Saitou ,  Akitaka Murata ,  Hiroyuki Ban ,  Tadashi Suzuki ,  Toshio Sakakibara ,  Takayuki Sugisaka ,  Shoji Miura

发明人： Makio Iida ,  Mitsuhiro Saitou ,  Akitaka Murata ,  Hiroyuki Ban ,  Tadashi Suzuki ,  Toshio Sakakibara ,  Takayuki Sugisaka ,  Shoji Miura

IPC分类号： H01L21/762 ,  H01L29/36

CPC分类号： H01L21/76264

摘要： A semiconductor device including a semiconductor substrate having a main surface. An insulating film is formed on the main surface of the semiconductor substrate. A semiconductor layer is placed on the insulating film. Side insulating regions extending from a surface of the semiconductor layer to the insulating film divide the semiconductor layer into element regions. The element regions are isolated from each other by the side insulating regions and the insulating film. The semiconductor substrate has a resistivity of 1.5 .OMEGA.cm or lower. A voltage at the semiconductor substrate is set to a given voltage.

摘要翻译： 一种半导体器件，包括具有主表面的半导体衬底。 绝缘膜形成在半导体衬底的主表面上。 半导体层被放置在绝缘膜上。 从半导体层的表面延伸到绝缘膜的侧绝缘区域将半导体层分成元件区域。 元件区域通过侧绝缘区域和绝缘膜彼此隔离。 半导体基板的电阻率为1.5欧姆·厘米或更低。 将半导体衬底处的电压设定为给定电压。

公开(公告)号：US5599722A

公开(公告)日：1997-02-04

申请号：US346255

申请日：1994-11-23

申请人： Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

发明人： Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

IPC分类号： H01L21/02 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/265 ,  H01L21/302

CPC分类号： H01L21/76264 ,  H01L21/76275 ,  H01L21/76281 ,  H01L21/76286

摘要： A trench isolation junction type SOI semiconductor device which reduces substrate warpage while suppressing increase in production steps and a method for producing the same are disclosed. A junction substrate is formed by bonding a semiconductor substrate having an outer insulation film on a non-junction main surface with a semiconductor layer with an inner insulation film sandwiched therebetween. After forming a silicon nitride film as a mask for the purpose of forming a trench in the semiconductor layer, silicon nitride film accumulated on the outer insulation film is removed. By doing this, warpage of the semiconductor substrate due to discrepancies in the thermal expansion rates of the rigid silicon nitride film and semiconductor substrate can be prevented. In a junction type SOI semiconductor device formed via the method, an outer insulation film of identical thickness and identical density to an inner insulation film is formed on a non-junction main surface (i.e., rear surface) of a semiconductor substrate. By doing this, warpage of the semiconductor substrate can be prevented.

摘要翻译： 公开了一种在抑制生产步骤增加的同时降低衬底翘曲的沟槽隔离结型SOI半导体器件及其制造方法。 通过在非接合主表面上具有外绝缘膜的半导体衬底与夹在其间的内绝缘膜的半导体层结合来形成接合衬底。 在形成用于在半导体层中形成沟槽的掩模的氮化硅膜之后，除去积聚在外绝缘膜上的氮化硅膜。 通过这样做，可以防止由于刚性氮化硅膜和半导体衬底的热膨胀率的差异导致的半导体衬底的翘曲。 在通过该方法形成的结型SOI半导体器件中，在半导体衬底的非接合主表面（即后表面）上形成具有相同厚度和与内绝缘膜相同密度的外绝缘膜。 通过这样做，可以防止半导体衬底的翘曲。

公开(公告)号：US5592015A

公开(公告)日：1997-01-07

申请号：US547740

申请日：1995-10-26

申请人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

发明人： Makio Iida ,  Tadashi Shibata ,  Takayuki Sugisaka ,  Shoji Miura ,  Toshio Sakakibara

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/762 ,  H01L21/763 ,  H01L27/02 ,  H01L29/732 ,  H01L29/00 ,  H01L23/58

CPC分类号： H01L29/7322 ,  H01L21/76264 ,  H01L21/763 ,  H01L27/0248 ,  H01L21/76286

摘要： A semiconductor device is provided which makes a high withstand voltage bipolar transistor small and prevents deterioration in a switching speed of the transistor. A silicon oxide layer is formed on a silicon substrate, and a semiconductor island of one conductivity type which is isolated laterally by an isolation trench is formed on the silicon oxide layer. A silicon oxide film is formed on an outer periphery portion of the semiconductor island to bury the trench. In the semiconductor island, a bipolar transistor, namely a base region of the other conductivity type, is formed, and in the base region an emitter region of one conductivity type is formed and a collector region of one conductivity type is further formed. In the semiconductor island a diffusion region of the other conductivity type for extracting excessive carriers to which a constant electric potential is applied is further formed.

摘要翻译： 提供一种半导体器件，其使得高耐压双极晶体管变小，并防止晶体管的开关速度的劣化。 在硅衬底上形成硅氧化物层，在氧化硅层上形成由隔离沟侧向隔离的一种导电型半导体岛。 在半导体岛的外周部形成有氧化硅膜，以埋置沟槽。 在半导体岛中，形成双极晶体管，即另一种导电型的基极区域，在基极区域形成一个导电型的发射极区域，并进一步形成一种导电型的集电极区域。 在半导体岛中，进一步形成用于提取施加恒定电位的过量载流子的另一导电类型的扩散区域。

公开(公告)号：US5557134A

公开(公告)日：1996-09-17

申请号：US341977

申请日：1994-11-16

申请人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

发明人： Takayuki Sugisaka ,  Toshio Sakakibara ,  Shoji Miura ,  Makio Iida

IPC分类号： H01L21/322 ,  H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/763 ,  H01L29/73 ,  H01L29/732 ,  H01L29/866 ,  H01L29/00

CPC分类号： H01L21/76264 ,  H01L21/3226 ,  H01L21/763 ,  H01L29/7317 ,  H01L29/732 ,  H01L21/76275 ,  H01L21/76286

摘要： A dielectric isolated type semiconductor device which can achieve a reduction in crystalline defects by means of a simple production process is provided. High-concentration regions are formed as active regions on a surface portion of an islandish semiconductor region which is isolated from an adjacent semiconductor region by means of an isolation trench. According to a first aspect of the present invention, an N type crystalline defect suppression region doped at a high concentration and deeper than the high-concentration regions is formed over the entire surface of an adjacent semiconductor region. According to a second aspect of the present invention, a high-concentration N type crystalline defect suppression region is provided on a surface portion of a P type high-concentration region is formed with identical structure and by an identical production process. By means of these N type regions, crystalline defects are reduced.

摘要翻译： 提供了一种能够通过简单的制造工艺实现结晶缺陷降低的绝缘隔离型半导体器件。 在通过隔离沟槽与相邻的半导体区域隔离的岛状半导体区域的表面部分上形成高浓度区域作为有源区域。 根据本发明的第一方面，在相邻的半导体区域的整个表面上形成了在高浓度区域和高浓度区域掺杂的N型晶体缺陷抑制区域。 根据本发明的第二方面，在P型高浓度区域的表面部分上形成高浓度的N型结晶缺陷抑制区域，其结构相同，生产方法相同。 通过这些N型区域，晶体缺陷减少。