公开(公告)号：US20170091037A1

公开(公告)日：2017-03-30

申请号：US15282254

申请日：2016-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Ron Diamant ,  Nafea Bshara ,  Yaniv Shapira ,  Guy Nakibly

IPC: G06F11/10 ,  G06F11/20

CPC classification number: G06F11/1092 ,  G06F11/1076 ,  G06F11/1096 ,  G06F11/2094 ,  G06F2211/1057

Abstract: A method for calculating a plurality (M) of redundancy blocks for multiple (N) data blocks of a plurality (D) of words each, the method comprises: receiving the number (M) of redundancy blocks by a calculator that comprises multiple (R) calculation units; configuring the calculator according to M and R; concurrently calculating, if M equals R, by the multiple (R) calculation units of the calculator, R sets of parity vectors, each set includes a plurality (D) of parity vectors; and calculating the plurality (M) of the redundancy blocks based on the R sets of parity vectors.

公开(公告)号：US12271511B1

公开(公告)日：2025-04-08

申请号：US17805671

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Moshe Raz ,  Zvika Glaubach

IPC: G06F21/75

Abstract: Techniques for cooperative timing alignment using synchronization pulses are described. The techniques can include generating, at an integrated circuit device, a timing signal, controlling a local count value based on the timing signal, monitoring a synchronization signal of a system comprising the integrated circuit device, detecting a synchronization pulse in the synchronization signal, and aligning the local count value with an implied count value associated with the synchronization pulse in order to align the local count value with those of other integrated circuit devices of the system.

公开(公告)号：US20240126705A1

公开(公告)日：2024-04-18

申请号：US18538699

申请日：2023-12-13

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F13/10 ,  G06F9/50 ,  G06F13/24 ,  G06F13/42

CPC classification number: G06F13/105 ,  G06F9/5077 ,  G06F13/24 ,  G06F13/4282 ,  G06F2213/0026 ,  G06F2213/0058

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers in an integrated circuit device for a set of functions corresponding to a type of peripheral device. The type of peripheral device represented by the integrated circuit device can be modified by changing the set of configuration registers being emulated in the integrated circuit device. Multiple sets of configuration registers can also be emulated to support different virtual machines or different operating systems.

公开(公告)号：US11960392B1

公开(公告)日：2024-04-16

申请号：US17643127

申请日：2021-12-07

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Dan Saad ,  Yaniv Shapira ,  Erez Izenberg

IPC: G06F13/14 ,  G06F9/46 ,  G06F12/02 ,  G06F13/16 ,  G06F13/38 ,  G06F13/42 ,  G11C11/408

CPC classification number: G06F12/0238 ,  G06F9/467 ,  G06F12/0292 ,  G06F13/1621 ,  G06F13/38 ,  G06F13/4221 ,  G11C11/4087

Abstract: A first configurable address decoder can be coupled between a source node and a first interconnect fabric, and a second address decoder can be coupled between the first interconnect fabric and a second interconnect fabric. The first address decoder can be configured with a first address mapping table that can map a first set of address ranges to a first set of target nodes connected to the first interconnect fabric. The second address decoder can be configured with a second address mapping table that can map a second set of address ranges to a second set of target nodes connected to the second interconnect fabric. The second address decoder can be part of the first set of target nodes. The first address decoder and the second address decoder can be configured or re-configured to determine different routes for a transaction from the source node to a target node in the second set of target nodes via the first and second interconnect fabrics.

公开(公告)号：US11899969B1

公开(公告)日：2024-02-13

申请号：US17805633

申请日：2022-06-06

Applicant: Amazon Technologies, Inc.

Inventor： Barak Singer ,  Guy Nakibly ,  Jonathan Cohen ,  Simaan Bahouth

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0604 ,  G06F3/0679

Abstract: Techniques are described for maintaining in-order execution when a dependency exists between write transactions. In some embodiments, a write re-order buffer (WROB) is configured to assign the same group ID to an incoming write transaction upon determining that the incoming write transaction is dependent on a pending write transaction. The WROB forwards the incoming write transaction to an interconnect fabric for routing to a completer device. The interconnect fabric enforces in-order execution when write transactions share the same group ID. The WROB can maintain a transaction log of pending write transactions and also track the statuses of responses for such transactions. Transaction responses can include responses sent from a completer to confirm that a transaction has actually been completed. Additionally, the WROB can send a response indicating completion back to the requester of the transaction. In some embodiments, the WROB is configured to send an early response to the requester.

公开(公告)号：US11860781B1

公开(公告)日：2024-01-02

申请号：US17662062

申请日：2022-05-04

Applicant: Amazon Technologies, Inc.

Inventor： Moshe Raz ,  Guy Nakibly ,  Gal Avisar

IPC: G06F12/00 ,  G06F12/0802 ,  G06F3/06

CPC classification number: G06F12/0802 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0673 ,  G06F2212/60

Abstract: A write cleaner circuit can be used to implement write-through (WT) functionality by a write-back (WB) cache memory for updating the system memory. The write cleaner circuit can intercept memory write transactions issued to the WB cache memory and generate clean requests that can enable the WB cache memory to send update requests to corresponding memory locations in the system memory around the same time as the memory write transactions are performed by the WB cache memory, and clear dirty bits in the cache lines corresponding to those memory write transactions.

公开(公告)号：US11853253B1

公开(公告)日：2023-12-26

申请号：US14983335

申请日：2015-12-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Guy Nakibly

IPC: G06F15/173 ,  H04L67/1097

CPC classification number: G06F15/17331 ,  H04L67/1097

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

公开(公告)号：US20230409514A1

公开(公告)日：2023-12-21

申请号：US18239694

申请日：2023-08-29

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Leah Shalev ,  Erez Izenberg ,  Georgy Machulsky ,  Guy Nakibly

IPC: G06F15/173 ,  H04L67/1097

CPC classification number: G06F15/17331 ,  H04L67/1097

Abstract: Apparatus and methods are disclosed herein for remote, direct memory access (RDMA) technology that enables direct memory access from one host computer memory to another host computer memory over a physical or virtual computer network. In one example, RDMA functionality is provided by combining a host executing instructions for RDMA software applications with dedicated hardware accelerator, where the host has access to substantially all RDMA connection context (e.g., configuration, status, state machine, counters, etc.) and a hardware accelerator stores a portion of the context information for a set of currently active transactions. The hardware accelerator derives a transaction identifier from header information in received RDMA packets and performs a local RDMA operation using at least a portion of the received data, a destination address of the location RDMA operation being based at least in part on a memory address determined using the transaction identifier.

公开(公告)号：US11640366B1

公开(公告)日：2023-05-02

申请号：US17457812

申请日：2021-12-06

Applicant: Amazon Technologies, Inc.

Inventor： Dan Saad ,  Guy Nakibly ,  Yaniv Shapira ,  Aviv Bonomo ,  Moshe Gutman

IPC: G06F13/362 ,  G06F13/42 ,  G06F13/40 ,  G06F15/78 ,  G06F9/46

Abstract: An address decoder for a source node in a multi-chip system is disclosed, which can perform parallel decoding steps to determine whether a transaction from the source node is addressed to a target node in a local integrated circuit (IC) or a remote IC, and whether the source node is allowed to access that target node. Based on the outcome of both the decoding steps, the transaction can be either blocked by the address decoder, or routed to the target node. If the transaction is addressed to the remote IC, but the source node is not allowed to access the target node on the remote IC, the transaction can be terminated by the address decoder in the local IC.

公开(公告)号：US20190215021A1

公开(公告)日：2019-07-11

申请号：US16241275

申请日：2019-01-07

Applicant: Amazon Technologies, Inc.

Inventor： Ofer Frishman ,  Erez Izenberg ,  Guy Nakibly

IPC: H03M13/00 ,  G06F12/0813 ,  H03M13/09 ,  H04L29/06 ,  G06F11/10 ,  G06F12/12

Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.