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公开(公告)号：US20180358103A1
公开(公告)日：2018-12-13
申请号：US15992229
申请日：2018-05-30
Applicant: Apple Inc.
Inventor： Yael Shur , Assaf Shappir , Barak Baum , Roman Guy , Michael Tsohar
CPC classification number: G11C16/3495 , G11C16/08 , G11C16/10 , G11C16/3418
Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
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公开(公告)号：US10008278B1
公开(公告)日：2018-06-26
申请号：US15619494
申请日：2017-06-11
Applicant: Apple Inc.
Inventor： Yael Shur , Assaf Shappir , Barak Baum , Roman Guy , Michael Tsohar
CPC classification number: G11C16/3495 , G11C16/08 , G11C16/10 , G11C16/3418
Abstract: A storage device includes storage circuitry and multiple memory blocks. The multiple memory blocks are arranged in an array, and each of the memory blocks includes multiple memory cells. A maximal number of programming cycles that a memory block of the multiple memory blocks sustains depends on a distance of the memory block from an edge of the array. The storage circuitry is configured to apply to the memory blocks programming cycles so that a number of programming cycles that can be applied to a respective memory block is based on a respective distance of the respective memory block from the edge of the array.
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公开(公告)号：US20170262033A1
公开(公告)日：2017-09-14
申请号：US15220411
申请日：2016-07-27
Applicant: APPLE INC.
Inventor： Barak Rotbard , Assaf Shappir
CPC classification number: G06F1/263 , G06F1/3225 , G06F3/0634 , G11C5/14 , G11C5/145 , G11C5/148 , G11C16/30
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
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公开(公告)号：US20200005873A1
公开(公告)日：2020-01-02
申请号：US16202127
申请日：2018-11-28
Applicant: Apple Inc.
Inventor： Eli Yazovitsky , Assaf Shappir , Itay Sagron , Meir Dalal
Abstract: A storage device includes storage circuitry and multiple memory cells. The memory cells are organized in multiple memory blocks of a nonvolatile memory. The storage circuitry is configured to define a partial verification scheme that specifies testing only a data portion of the data programmed to the memory blocks, to program data to a memory block, calculate redundancy data over the data, and save the calculated redundancy data in a dedicated memory, to verify that the data portion specified for the memory block in the partial verification scheme has been programmed successfully, to check a predefined condition for conditionally performing full verification to the memory block, when the predefined condition is fulfilled, to verify that data programmed to the memory block and not tested using the partial verification scheme has been programmed successfully, and to recover, using the redundancy data, at least part of the data programmed that failed verification.
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Patent Agency Ranking
公开(公告)号：US10339324B2
公开(公告)日：2019-07-02
申请号：US15387699
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Assaf Shappir , Itay Sagron
IPC: G06F21/60 , G11C11/56 , G06F21/86 , G06F21/75 , G06F21/62 , G06F21/79 , G11C7/24 , G11C16/22 , G11C29/50 , G11C29/44
Abstract: An apparatus includes an interface and storage circuitry. The interface is configured to communicate with a memory including multiple memory cells that store data as respective analog values. The memory is addressable using physical addresses. The storage circuitry is configured to perform a first read operation from a physical address, and determine a first sequence of analog values retrieved by the first read operation, to further perform a second read operation from the physical address, and determine a second sequence of analog values retrieved by the second read operation, to evaluate a variation between the first sequence and the second sequence, and to determine that an unauthorized re-programming to the physical address has occurred between the first read operation and the second read operation, in response to the evaluated variation exceeding a predefined variation level.
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公开(公告)号：US20180173285A1
公开(公告)日：2018-06-21
申请号：US15898586
申请日：2018-02-18
Applicant: Apple Inc.
Inventor： Barak Rotbard , Assaf Shappir
CPC classification number: G06F1/263 , G06F1/3225 , G06F3/0634 , G11C5/14 , G11C5/145 , G11C5/148 , G11C16/30
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
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公开(公告)号：US09996417B2
公开(公告)日：2018-06-12
申请号：US15096303
申请日：2016-04-12
Applicant: Apple Inc.
Inventor： Assaf Shappir , Etai Zaltsman , Guy Ben-Yehuda
CPC classification number: G06F11/1072 , G06F11/108 , G11C29/52
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
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公开(公告)号：US09898059B2
公开(公告)日：2018-02-20
申请号：US15220411
申请日：2016-07-27
Applicant: APPLE INC.
Inventor： Barak Rotbard , Assaf Shappir
CPC classification number: G06F1/263 , G06F1/3225 , G06F3/0634 , G11C5/14 , G11C5/145 , G11C5/148 , G11C16/30
Abstract: A memory controller includes an interface and a processor. The interface is configured to communicate with one or more memory devices that require an operation voltage. The memory devices are capable of obtaining the operation voltage either from a power supply external to the memory device or from respective charge pumps internal to the memory devices. The processor is configured to predict storage activity in the memory devices, and to cause the memory devices to select a source for the operation voltage between the power supply and the respective charge pumps in accordance with the predicted storage activity.
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公开(公告)号：US20170293527A1
公开(公告)日：2017-10-12
申请号：US15096303
申请日：2016-04-12
Applicant: Apple Inc.
Inventor： Assaf Shappir , Etai Zaltsman , Guy Ben-Yehuda
CPC classification number: G06F11/1072 , G06F11/108 , G11C29/52
Abstract: A controller includes an interface and a processor. The interface is configured to communicate with a memory including multiple memory cells organized in at least two sections each including multiple sets of word lines (WLs), wherein in a first failure mode multiple WLs fail in a single section, and in a second failure mode a WL fails in multiple sections. The processor is configured to assign multiple cell-groups of the memory cells to a parity-group, such that (i) no two cell-groups in the parity-group belong to a same WL, and (ii) no two cell-groups in the parity-group belong to adjacent WLs in a same section, and, upon detecting a failure to access a cell-group in the parity-group, due to either the first or second failure modes but not both failure modes occurring simultaneously, to recover the data stored in the cell-group using one or more remaining cell-groups in the parity-group.
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