公开(公告)号：US10224873B1

公开(公告)日：2019-03-05

申请号：US15377004

申请日：2016-12-13

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Rashed Mahameed ,  Brad W. Simeral

IPC: H02K33/18 ,  H02N2/18 ,  H03B5/12

Abstract: In various embodiments, a voltage collection bootstrap circuit includes a capacitor, an inductor, an oscillator, a bias circuit, and a switch. A current may be induced in the inductor, the oscillator, or both. The inductor, the oscillator, or both may store energy in the capacitor. The inductor, capacitor, and oscillator may supply energy to the bias circuit. The bias circuit may output a difference between a reference voltage and a voltage corresponding to the energy received from at least one of the inductor, capacitor, and oscillator. Based on the output of the bias circuit, a switch may connect the voltage collection circuit to an output of at least one of the inductor, capacitor, and oscillator. Accordingly, energy may be provided to the voltage collection circuit using one or more induced currents.

公开(公告)号：US20170083069A1

公开(公告)日：2017-03-23

申请号：US14858035

申请日：2015-09-18

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Jafar Savoj ,  Inder M. Sodhi ,  Cyril de la Cropte de Chanterac ,  Sotirios Zogopoulos

IPC: G06F1/28 ,  G01R19/25 ,  G06F1/26 ,  G01R19/255

CPC classification number: G06F1/28 ,  G01R19/2506 ,  G01R19/255 ,  G06F1/26 ,  G06F1/263

Abstract: An apparatus for determining an average current through an inductor of a regulator circuit is disclosed. A counter unit may be configured to receive a control signal, which includes a plurality of pulses, from a Power Management Unit (PMU), and determine a number of pulses received during a predetermined period of time. A pulse sampler unit may determine a duration of a given pulse of the plurality of pulses. Circuitry may be configured to determine the average current through the inductor during the predetermined period of time dependent upon the number of pulses received during the predetermined period of time and the duration of the given pulse.

公开(公告)号：US20250167048A1

公开(公告)日：2025-05-22

申请号：US19028523

申请日：2025-01-17

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L21/77 ,  H01L21/66 ,  H01L23/00 ,  H01L25/03 ,  H01L25/16 ,  H01L25/18

Abstract: A disclosed system includes a package body that includes a system-on-a-chip (SoC) and an interconnect region. In an embodiment, the interconnect region includes a first conductive path between the SoC and a voltage regulator module (VRM), a second conductive path between the SoC and a first external connection, and a third conductive path between the VRM and a second external connection. In another embodiment, the VRM is positioned between and coupled to a first portion of the SoC and a first surface of the interconnect region. A second portion of the SoC is coupled directly to the first surface of the interconnection region. In another embodiment, the interconnect region has first and second opposing surfaces. The SoC is positioned on the first surface of the interconnect region. The VRM is externally coupled to a first surface of the package body adjacent to the second surface of the interconnect region.

公开(公告)号：US20240160268A1

公开(公告)日：2024-05-16

申请号：US18523819

申请日：2023-11-29

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

公开(公告)号：US11868192B2

公开(公告)日：2024-01-09

申请号：US17528380

申请日：2021-11-17

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Keith Cox ,  Gerard R. Williams, III

IPC: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

CPC classification number: G06F1/3206 ,  G06F1/3203 ,  G06F1/3296

Abstract: In an embodiment, a system includes multiple power management mechanism operating in different time domains (e.g., with different bandwidths) and control circuitry that is configured to coordinate operation of the mechanisms. If one mechanism is adding energy to the system, for example, the control circuitry may inform another mechanism that the energy is coming so that the other mechanism may not take as drastic an action as it would if no energy were coming. If a light workload is detected by circuitry near the load, and there is plenty of energy in the system, the control circuitry may cause the power management unit (PMU) to generate less energy or even temporarily turn off. A variety of mechanisms for the coordinated, coherent use of power are described.

公开(公告)号：US10818632B1

公开(公告)日：2020-10-27

申请号：US15943673

申请日：2018-04-02

Applicant: Apple Inc.

Inventor： Vidhya Ramachandran ,  Jun Zhai ,  Chonghua Zhong ,  Kunzhong Hu ,  Shawn Searles ,  Joseph T. DiBene, II ,  Mengzhi Pang

IPC: H01L23/00 ,  H01L21/66 ,  H01L21/77

Abstract: Systems that include integrated circuit dies and voltage regulator units are disclosed. Such systems may include a voltage regulator module and an integrated circuit mounted in a common system package. The voltage regulator module may include a voltage regulator circuit and one or more passive devices mounted to a common substrate, and the integrated circuit may include a System-on-a-chip. The system package may include an interconnect region that includes wires fabricated on multiple conductive layers within the interconnect region. At least one power supply terminal of the integrated circuit may be coupled to an output of the voltage regulator module via a wire included in the interconnect region.

公开(公告)号：US20190212796A1

公开(公告)日：2019-07-11

申请号：US16360194

申请日：2019-03-21

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  Inder M. Sodhi ,  Gerard R. Williams, III

IPC: G06F1/26 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

CPC classification number: G06F1/263 ,  G06F1/26 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: In an embodiment, a system may support a “coast mode” in which the power management unit (PMU) that supplies the supply voltage to an integrated circuit is disabled temporarily for certain modes of the integrated circuit. The integrated circuit may continue to operate, consuming the energy stored in capacitance in and/or around the integrated circuit. When coast mode is initiated, a time interval for coasting may be determined. When the time interval expires, the PMU may re-enable the power supply voltage.

公开(公告)号：US10209767B2

公开(公告)日：2019-02-19

申请号：US15168472

申请日：2016-05-31

Applicant: Apple Inc.

Inventor： Joseph T. DiBene, II ,  David A. Hartley ,  Inder M. Sodhi

IPC: G06F1/32 ,  G06F9/32 ,  G06F9/38

Abstract: In one embodiment, an integrated circuit includes a power management architecture in which one or more pipelines are actively powered and clocked when data is provided for processing, but which are clock gated and in retention when there is no data to be processed. When data is provided to the pipeline, supply voltage may be actively provided to initial stages of the pipeline and the clocks may be ungated when the voltage is stable enough for operation. Subsequent stages of the pipeline may be sequentially provided power and clocks as the data progresses through the pipeline. Initial stages may be clock gated and power may be deactivated when additional data is not provided for processing. Accordingly, when the pipeline is viewed as a whole, power may be seen as rolling forward ahead of the data processing, and power may be inhibited in a similar rolling fashion.

公开(公告)号：US09825620B2

公开(公告)日：2017-11-21

申请号：US15002495

申请日：2016-01-21

Applicant: Apple Inc.

Inventor： Sotirios Zogopoulos ,  Joseph T. DiBene, II ,  Jafar Savoj

IPC: G06F1/20 ,  H03K5/19 ,  H03K3/03 ,  H03K5/02 ,  H03K5/24 ,  H03K5/26 ,  G06F1/32 ,  G06F1/26 ,  G06F1/28 ,  G06F1/30

CPC classification number: H03K5/19 ,  G06F1/26 ,  G06F1/28 ,  G06F1/30 ,  G06F1/305 ,  G06F1/3206 ,  G06F1/324 ,  H03K3/0315 ,  H03K5/02 ,  H03K5/24 ,  H03K5/26 ,  Y02D10/126

Abstract: A method and apparats for undervoltage detection and correction is disclosed. An IC includes sensors implemented in various functional circuit blocks. The sensors are implemented using ring oscillators, and may be characterized by a polynomial. The sensors are used to monitor a supply voltage provided to a corresponding functional unit. The sensors provide information indicative of the voltage on the supply voltage node over successive clock cycles. Comparison circuitry may be used to compare the detected voltage to one or more voltage thresholds, while delta comparison circuitry may be used to determine a slope, or rate of change of the voltage. Based on comparisons performed by the comparison circuitry and the delta comparison circuitry, control circuitry may determine if one or more voltage correction actions are to be taken in order to bring the voltage on the supply node into a specified range.

公开(公告)号：US20170214399A1

公开(公告)日：2017-07-27

申请号：US15002495

申请日：2016-01-21

Applicant: Apple Inc.

Inventor： Sotirios Zogopoulos ,  Joseph T. DiBene, II ,  Jafar Savoj

IPC: H03K5/19 ,  H03K5/02 ,  H03K3/03 ,  H03K5/24 ,  H03K5/26

CPC classification number: H03K5/19 ,  G06F1/26 ,  G06F1/28 ,  G06F1/30 ,  G06F1/305 ,  G06F1/3206 ,  G06F1/324 ,  H03K3/0315 ,  H03K5/02 ,  H03K5/24 ,  H03K5/26 ,  Y02D10/126

Abstract: A method and apparats for undervoltage detection and correction is disclosed. An IC includes sensors implemented in various functional circuit blocks. The sensors are implemented using ring oscillators, and may be characterized by a polynomial. The sensors are used to monitor a supply voltage provided to a corresponding functional unit. The sensors provide information indicative of the voltage on the supply voltage node over successive clock cycles. Comparison circuitry may be used to compare the detected voltage to one or more voltage thresholds, while delta comparison circuitry may be used to determine a slope, or rate of change of the voltage. Based on comparisons performed by the comparison circuitry and the delta comparison circuitry, control circuitry may determine if one or more voltage correction actions are to be taken in order to bring the voltage on the supply node into a specified range.