公开(公告)号：US11894233B2

公开(公告)日：2024-02-06

申请号：US17955996

申请日：2022-09-29

Applicant: Applied Materials, Inc.

Inventor： Yixiong Yang ,  Wei V. Tang ,  Seshadri Ganguli ,  Sang Ho Yu ,  Feng Q. Liu ,  Jeffrey W. Anthis ,  David Thompson ,  Jacqueline S. Wrench ,  Naomi Yoshida

IPC: H01L21/285 ,  C23C16/455 ,  C23C16/18 ,  H01L23/532 ,  C23C16/04

CPC classification number: H01L21/28562 ,  C23C16/04 ,  C23C16/18 ,  C23C16/45553 ,  H01L21/28518 ,  H01L21/28568 ,  H01L23/53242

Abstract: Methods of depositing platinum group metal films of high purity, low resistivity, and good conformality are described. A platinum group metal film is formed in the absence of an oxidant. The platinum group metal film is selectively deposited on a conductive substrate at a temperature less than 200° C. by using an organic platinum group metal precursor.

公开(公告)号：US20230369031A1

公开(公告)日：2023-11-16

申请号：US18127213

申请日：2023-03-28

Applicant: Applied Materials, Inc.

Inventor： Tomohiko Kitajima ,  Ning Li ,  Chang Seok Kang ,  Naomi Yoshida

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67 ,  C23C16/02 ,  C23C16/56 ,  C23C16/34 ,  C23C16/36 ,  C23C16/38

CPC classification number: H01J37/32899 ,  H01L21/0217 ,  H01L21/0234 ,  H01L21/67167 ,  C23C16/0227 ,  C23C16/56 ,  C23C16/345 ,  C23C16/36 ,  C23C16/38 ,  C23C16/342 ,  H01J2237/335 ,  H01J2237/332 ,  H01J2237/336 ,  H01J37/32816 ,  H01J2237/20278

Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.

公开(公告)号：US11145761B2

公开(公告)日：2021-10-12

申请号：US16592362

申请日：2019-10-03

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US10777650B2

公开(公告)日：2020-09-15

申请号：US15494981

申请日：2017-04-24

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Sheng-Chin Kung ,  Miao Jin

IPC: H01L27/12 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

Abstract: The present disclosure provides an apparatus and methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures includes depositing a dielectric material on a first side and a second side of a stack. The stack may include repeating pairs of a first layer and a second layer. The first side is opposite the second side and the first side and the second side have one or more recesses formed therein. The method includes removing the dielectric material from the first side and the second side of the stack. The dielectric material remains in the one or more recesses. The method includes the deposition of a stressor layer and the formation of one or more side gaps between the stressor layer and the first side and the second side of the stack.

公开(公告)号：US10177227B1

公开(公告)日：2019-01-08

申请号：US15687747

申请日：2017-08-28

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  Lin Dong ,  Shiyu Sun ,  Myungsun Kim ,  Nam Sung Kim ,  Dimitri Kioussis ,  Mikhail Korolik ,  Gaetano Santoro ,  Vanessa Pena

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/417 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: The present disclosure provides methods for forming horizontal gate-all-around (hGAA) structure devices. In one example, a method includes selectively and laterally etching a first group of sidewalls of a first layer in a multi-material layer, wherein the multi-material layer comprises repeating pairs of the first layer and a second layer, the first and the second layers having the first group and a second group of sidewalls respectively, the first group of sidewalls from the first layer exposed through openings defined in the multi-material layer and a group of inner spacers formed atop of the second group of sidewalls from the second layer, forming a recess from the first group of sidewalls of the first layer and defining a vertical wall inward from an outer vertical surface of the inner spacer formed atop of the second layers, and forming an epi-silicon layer from the recess of the first layer.

公开(公告)号：US10134585B2

公开(公告)日：2018-11-20

申请号：US14830131

申请日：2015-08-19

Applicant: The Regents of the University of California ,  GLOBALFOUNDRIES, Inc. ,  Applied Materials, Inc.

Inventor： Kasra Sardashti ,  Tobin Kaufman-Osborn ,  Tyler Kent ,  Andrew Kummel ,  Shariq Siddiqui ,  Bhagawan Sahu ,  Adam Brand ,  Naomi Yoshida

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/306 ,  H01L29/94

Abstract: Surface pretreatment of SiGe or Ge surfaces prior to gate oxide deposition cleans the SiGe or Ge surface to provide a hydrogen terminated surface or a sulfur passivated (or S—H) surface. Atomic layer deposition (ALD) of a high-dielectric-constant oxide at a low temperature is conducted in the range of 25-200° C. to form an oxide layer. Annealing is conducted at an elevated temperature. A method for oxide deposition on a damage sensitive III-V semiconductor surface conducts in-situ cleaning of the surface with cyclic pulsing of hydrogen and TMA (trimethyl aluminum) at a low temperature in the range of 100-200° C. Atomic layer deposition (ALD) of a high-dielectric-constant oxide forms an oxide layer. Annealing is conducted at an elevated temperature. The annealing can create a silicon terminated interfaces.

公开(公告)号：US10109534B2

公开(公告)日：2018-10-23

申请号：US14627861

申请日：2015-02-20

Applicant: APPLIED MATERIALS, INC.

Inventor： Adam Brand ,  Naomi Yoshida ,  Seshadri Ganguli ,  David Thompson ,  Mei Chang

IPC: H01L21/3205 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: Methods for forming a multi-threshold voltage device on a substrate are provided herein. In some embodiments, the method of forming a multi-threshold voltage device may include (a) providing a substrate having a first layer disposed thereon, wherein the substrate comprises a first feature and a second feature disposed within the first layer; (b) depositing a blocking layer atop the substrate; (c) selectively removing a portion of the blocking layer from atop the substrate to expose the first feature; (d) selectively depositing a first work function layer atop the first feature; (e) removing a remainder of the blocking layer to expose the second feature; and (f) depositing a second work function layer atop the first work function layer and the second feature.

公开(公告)号：US09865735B2

公开(公告)日：2018-01-09

申请号：US15152273

申请日：2016-05-11

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Theresa Kramer Guarini ,  Sung Won Jun ,  Vanessa Pena ,  Errol Antonio C. Sanchez ,  Benjamin Colombeau ,  Michael Chudzik ,  Bingxi Wood ,  Nam Sung Kim

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/78642

Abstract: Embodiments described herein generally relate to methods and device structures for horizontal gate all around (hGAA) isolation and fin field effect transistor (FinFET) isolation. A superlattice structure comprising different materials arranged in an alternatingly stacked formation may be formed on a substrate. In one embodiment, at least one of the layers of the superlattice structure may be oxidized to form a buried oxide layer adjacent the substrate.

公开(公告)号：US09484406B1

公开(公告)日：2016-11-01

申请号：US14874146

申请日：2015-10-02

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Naomi Yoshida ,  Bingxi Wood

IPC: H01L29/423 ,  H01L29/06 ,  H01L21/02 ,  H01L29/165 ,  H01L29/41

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/0206 ,  H01L21/02126 ,  H01L21/0214 ,  H01L21/02167 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/0228 ,  H01L21/0231 ,  H01L21/67207 ,  H01L29/165 ,  H01L29/401 ,  H01L29/413 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775

Abstract: The present disclosure provide methods for forming nanowire structures with desired materials horizontal gate-all-around (hGAA) structures field effect transistor (FET) for semiconductor chips. In one example, a method of forming nanowire structures on a substrate includes supplying an oxygen containing gas mixture to a multi-material layer on a substrate in a processing chamber, wherein the multi-material layer includes repeating pairs of a first layer and a second layer, the first and the second layers having a first group and a second group of sidewalls respectively exposed through openings defined in the multi-material layer, and selectively forming an oxidation layer on the second group of sidewalls in the second layer.

Abstract translation: 本公开提供用于形成具有期望材料的纳米线结构的方法，用于半导体芯片的水平栅极全周（hGAA）结构场效应晶体管（FET）。 在一个实例中，在衬底上形成纳米线结构的方法包括将氧含气体混合物供应到处理室中的衬底上的多材料层，其中多材料层包括重复的第一层和第二层 所述第一和第二层分别具有通过限定在所述多层材料层中的开口暴露的第一组和第二组侧壁，并且在所述第二层中的所述第二侧壁组上选择性地形成氧化层。

公开(公告)号：US11848369B2

公开(公告)日：2023-12-19

申请号：US17672788

申请日：2022-02-16

Applicant: Applied Materials, Inc.

Inventor： Shiyu Sun ,  Nam Sung Kim ,  Bingxi Sun Wood ,  Naomi Yoshida ,  Sheng-Chin Kung ,  Miao Jin

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/02 ,  H01L29/775 ,  H01L29/786 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L29/42392 ,  H01L21/02603 ,  H01L29/0653 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78684 ,  H01L29/78696 ,  H01L29/0673

Abstract: Embodiments provide methods for forming nanowire structures, such as, for example, horizontal gate-all-around (hGAA) structures. In one embodiment, a method includes selectively etching material from a stack disposed on a material layer located on a substrate with a plasma to create recesses on each of first and second sides of the stack and depositing a dielectric material on the first and second sides. The stack includes repeating pairs of first and second layers. The method also includes removing the dielectric material from the first and second sides, where the dielectric material remains in the recesses of the first and second sides, and selectively depositing a stressor layer on regions of the first and second sides which are unprotected by the dielectric material to form gaps between the stressor layer and the dielectric material remaining in the recesses of the first and second sides.