公开(公告)号：US20210158865A1

公开(公告)日：2021-05-27

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes VAN WINKELHOFF ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

公开(公告)号：US11004503B1

公开(公告)日：2021-05-11

申请号：US16698866

申请日：2019-11-27

Applicant: Arm Limited

Inventor： Lalit Gupta ,  El Mehdi Boujamaa ,  Nicolaas Klarinus Johannes Van Winkelhoff ,  Bo Zheng ,  Fakhruddin Ali Bohra ,  Nimish Sharma ,  Hetansh Pareshbhai Shah

IPC: G11C11/419 ,  G11C11/16 ,  G11C11/418

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.

公开(公告)号：US10748583B2

公开(公告)日：2020-08-18

申请号：US15851341

申请日：2017-12-21

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C7/08 ,  G11C7/12 ,  G11C7/22

Abstract: Various implementations described herein are directed to an integrated circuit having first dummy bitline circuitry with a first charge storage element and second dummy bitline circuitry coupled to the first dummy bitline circuitry, and the second dummy bitline circuitry has a second charge storage element. The integrate circuit may include decoupling circuitry coupled to the first dummy bitline circuitry and the second dummy bitline circuitry between the first charge storage element and the second charge storage element. The decoupling circuitry may operate to decouple the second charge storage element from the first charge storage element based on an enable signal.

公开(公告)号：US10734065B2

公开(公告)日：2020-08-04

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419 ,  G11C7/12 ,  G11C8/16

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

公开(公告)号：US20200219559A1

公开(公告)日：2020-07-09

申请号：US16820487

申请日：2020-03-16

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/419

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US10600477B2

公开(公告)日：2020-03-24

申请号：US15960475

申请日：2018-04-23

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

公开(公告)号：US20190237111A1

公开(公告)日：2019-08-01

申请号：US15881704

申请日：2018-01-26

Applicant: Arm Limited

Inventor： Vivek Nautiyal ,  Satinderjit Singh ,  Abhishek B. Akkur ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra ,  Jungtae Kwon ,  Jitendra Dasani ,  Manoj Puthan Purayil

IPC: G11C5/06 ,  G11C7/06

CPC classification number: G11C5/063 ,  G11C7/06

Abstract: Various implementations described herein are directed to an integrated circuit having multiple banks of memory cells and a local input/output (IO) component for each bank of the multiple banks. The integrated circuit may include multiple signal lines that are coupled to the multiple banks with the local IO components. At least one signal line of the multiple signal lines is wider than one or more of the other signal lines.

公开(公告)号：US10056121B2

公开(公告)日：2018-08-21

申请号：US15451089

申请日：2017-03-06

Applicant: ARM Limited ,  The Regents of the University of Michigan

Inventor： Mahmood Khayatzadeh ,  Massimo Bruno Alioto ,  David Theodore Blaauw ,  Dennis Michael Chen Sylvester ,  Fakhruddin Ali Bohra

IPC: G11C7/00 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/065 ,  G11C5/063 ,  G11C7/06 ,  G11C7/1012 ,  G11C7/106 ,  G11C7/18 ,  G11C8/16 ,  G11C11/419 ,  G11C29/026 ,  G11C29/028 ,  G11C2207/002 ,  G11C2207/005

Abstract: Various implementations described herein may refer to and may be directed to circuitry for an integrated circuit using topology configurations. For instance, in one implementation, such circuitry may include a memory array having a plurality of memory cells. Such circuitry may also include one or more reconfigurable sense amplifier devices coupled to the memory array and configured to amplify differential voltage levels received from the memory array. The reconfigurable sense amplifier devices may include a plurality of sense amplifier circuits configured to be arranged in one of a plurality of topology configurations, where the topology configurations include a parallel configuration and a cross parallel configuration. The reconfigurable sense amplifier devices may also include one or more switches configured to set the plurality of sense amplifier circuits into the plurality of topological configurations based on one or more control bits.

公开(公告)号：US09583209B1

公开(公告)日：2017-02-28

申请号：US14963111

申请日：2015-12-08

Applicant: ARM Limited

Inventor： Rajiv Kumar Roy ,  Fakhruddin Ali Bohra ,  Manish Trivedi ,  Sumant Kumar Thapliyal ,  Vikash

IPC: G11C8/00 ,  G11C17/08

CPC classification number: G11C17/08 ,  G11C8/12

Abstract: Various implementations described herein are directed to an integrated circuit having high density memory architecture. The integrated circuit may include a plurality of bank arrays having multiple segments of bitcells configured to share local control. The integrated circuit may include a plurality of control lines coupling the local control to each of the multiple segments of bitcells. In some instances, during activation of a segment of bitcells by the local control via one of the control lines, another segment of bitcells may be deactivated by the local control via another of the control lines.

Abstract translation: 本文描述的各种实现涉及具有高密度存储器架构的集成电路。 集成电路可以包括具有被配置为共享本地控制的多个位单元段的多个存储体阵列。 集成电路可以包括将本地控制耦合到位单元的多个段中的每一个的多个控制线。 在一些情况下，在本地控制通过控制线之一激活位单元的段时，可以通过另一控制线的本地控制来停用另一段位单元。

公开(公告)号：US11776591B2

公开(公告)日：2023-10-03

申请号：US16584898

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Lalit Gupta ,  Bo Zheng ,  El Mehdi Boujamaa ,  Fakhruddin Ali Bohra

IPC: G11C7/10 ,  G11C11/419 ,  G11C11/16 ,  G11C11/418

CPC classification number: G11C7/1015 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/418 ,  G11C11/419

Abstract: Various implementations described herein refer to a method for providing single port memory with multiple different banks having a first bank and a second bank that is different than the first bank. The method may include coupling multiple wordlines to the single port memory including coupling a first wordline to the first bank and coupling a second wordline to the second bank. The method may include performing multiple memory access operations concurrently in the single port memory.