公开(公告)号：US20080197025A1

公开(公告)日：2008-08-21

申请号：US11090944

申请日：2005-03-25

Applicant: Yanxiu Zhou ,  Bin Yu ,  Kalle Levon

Inventor： Yanxiu Zhou ,  Bin Yu ,  Kalle Levon

IPC: G01N27/406

CPC classification number: C12Q1/6825 ,  C12Q2600/156 ,  G01N27/333 ,  C12Q2565/518

Abstract: Ionic interactions are monitored to detect hybridization. The measurement may be done measuring the potential change in the solution with the ion sensitive electrode (which may be the conducting polymer (e.g., polyaniline) itself), without applying any external energy during the binding. The double helix formation during the complimentary hybridization makes this electrode act as an ion selective electrode—the nucleotide hydrogen bonding is specific and thus monitoring the ionic phosphate group addition becomes selective. Polyaniline on the surface of nylon film forms a positively charged polymer film. Thiol linkage can be utilized for polyaniline modification and thiol-modified single strand oligonucleotide chains can be added to polyaniline. The sensitivity is because the double helix formation during the complimentary hybridization makes this electrode act as an ion selective electrode as the nucleotide hydrogen bonding is specific and thus monitoring the ionic phosphate group addition becomes selective.

Abstract translation: 监测离子相互作用以检测杂交。 测量可以通过离子敏感电极（其可以是导电聚合物（例如聚苯胺）本身））测量溶液中的潜在变化，而在结合期间不施加任何外部能量。 在互补杂交期间的双螺旋形成使得该电极用作离子选择性电极 - 核苷酸氢键是特异性的，因此监测离子性磷酸酯基添加成为选择性的。 尼龙膜表面的聚苯胺形成带正电的聚合物膜。 硫醇连接可用于聚苯胺改性，硫醇改性的单链寡核苷酸链可以加入到聚苯胺中。 敏感性是因为互补杂交期间的双螺旋形成使得该电极作为离子选择性电极，因为核苷酸氢键是特异性的，因此监测离子性磷酸酯基添加成为选择性的。

公开(公告)号：US20080054431A1

公开(公告)日：2008-03-06

申请号：US11513765

申请日：2006-08-31

Applicant: Tingqing Wang ,  Moon Wang ,  Bin Yu

Inventor： Tingqing Wang ,  Moon Wang ,  Bin Yu

IPC: H01L23/12 ,  H01L21/58

CPC classification number: H01L21/565 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L25/03 ,  H01L25/50 ,  H01L2224/32145 ,  H01L2224/45144 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2225/06568 ,  H01L2924/01079 ,  H01L2924/078 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A stacked chip semiconductor package may be formed in a “package in package” arrangement. The internal package may include two substrates. One substrate may have two dice stacked on each of two opposed sides and the other substrate may have two dice stacked on it as well. The two stacked substrates may be separated by molding compound and then electrically coupled to a third substrate. Thereafter, the entire assembly may be encapsulated.

Abstract translation: 堆叠式芯片半导体封装可以形成为“封装封装”布置。 内部封装可以包括两个基板。 一个基底可以具有两个堆叠在两个相对侧中的每一个上的骰子，另一个基底也可以在其上堆叠两个骰子。 两个堆叠的基板可以通过模制化合物分离，然后电耦合到第三基板。 此后，整个组件可以被封装。

公开(公告)号：US07235436B1

公开(公告)日：2007-06-26

申请号：US10614051

申请日：2003-07-08

Applicant: Ming-Ren Lin ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

Inventor： Ming-Ren Lin ,  Zoran Krivokapic ,  Haihong Wang ,  Bin Yu

IPC: H01L21/84

CPC classification number: H01L21/845 ,  H01L27/1211 ,  H01L29/66795 ,  H01L29/785

Abstract: A method for doping fin structures in FinFET devices includes forming a first glass layer on the fin structure of a first area and a second area. The method further includes removing the first glass layer from the second area, forming a second glass layer on the fin structure of the first area and the second area, and annealing the first area and the second area to dope the fin structures.

Abstract translation: 在FinFET器件中掺杂鳍结构的方法包括在第一区域和第二区域的鳍结构上形成第一玻璃层。 该方法还包括从第二区域去除第一玻璃层，在第一区域和第二区域的翅片结构上形成第二玻璃层，并退火第一区域和第二区域以掺杂翅片结构。

公开(公告)号：US07211489B1

公开(公告)日：2007-05-01

申请号：US10934378

申请日：2004-09-07

Applicant: Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

Inventor： Qi Xiang ,  Robert B. Ogle ,  Eric N. Paton ,  Cyrus E. Tabery ,  Bin Yu

IPC: H01L21/336

CPC classification number: H01L21/268 ,  H01L21/26506 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659

Abstract: The present invention enables the production of improved high-reliability, high-density semiconductor devices. The present invention provides the high-density semiconductor devices by decreasing the size of semiconductor device structures, such as gate channel lengths. Short-channel effects are prevented by the use of highly localized halo implant regions formed in the device channel. Highly localized halo implant regions are formed by a tilt pre-amorphization implant and a laser thermal anneal of the halo implant region.

Abstract translation: 本发明能够制造改进的高可靠性，高密度的半导体器件。 本发明通过减小诸如栅极沟道长度的半导体器件结构的尺寸来提供高密度半导体器件。 通过使用在器件通道中形成的高度局部化的注入区来防止短沟道效应。 通过倾斜预非晶化植入和晕圈植入区域的激光热退火形成高度局部化的注入区域。

公开(公告)号：US07196374B1

公开(公告)日：2007-03-27

申请号：US10653274

申请日：2003-09-03

Applicant: Ming-Ren Lin ,  Bin Yu

Inventor： Ming-Ren Lin ,  Bin Yu

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/78687

Abstract: A semiconductor device includes a substrate and an insulating layer on the substrate. The semiconductor device also includes a fin structure formed on the insulating layer, where the fin structure includes first and second side surfaces, a dielectric layer formed on the first and second side surfaces of the fin structure, a first gate electrode formed adjacent the dielectric layer on the first side surface of the fin structure, a second gate electrode formed adjacent the dielectric layer on the second side surface of the fin structure, and a doped structure formed on an upper surface of the fin structure in the channel region of the semiconductor device.

Abstract translation: 半导体器件包括衬底和衬底上的绝缘层。 半导体器件还包括形成在绝缘层上的翅片结构，其中鳍结构包括第一和第二侧表面，形成在鳍结构的第一和第二侧表面上的电介质层，形成在电介质层附近的第一栅电极 在翅片结构的第一侧表面上形成与鳍结构的第二侧表面上的电介质层相邻的第二栅电极，以及在半导体器件的沟道区中形成在鳍结构的上表面上的掺杂结构 。

公开(公告)号：US07183152B1

公开(公告)日：2007-02-27

申请号：US10975475

申请日：2004-10-29

Applicant: Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

Inventor： Srikanteswara Dakshina-Murthy ,  Chih-Yuh Yang ,  Bin Yu

IPC: H01L21/336 ,  H01L21/8234 ,  H01L21/00 ,  H01L21/84 ,  H01L21/3205

CPC classification number: H01L29/785 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/78687

Abstract: A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method includes growing a second material in the trench to form the fin and removing the layer of first material.

Abstract translation: 形成鳍状场效应晶体管（FinFET）的鳍片的方法包括在第一材料层中限定沟槽，其中沟槽的开口的宽度基本上小于该层的厚度。 该方法包括在沟槽中生长第二材料以形成翅片并去除第一材料层。

公开(公告)号：US07112847B1

公开(公告)日：2006-09-26

申请号：US10653227

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L27/01

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  Y10S257/90

Abstract: A semiconductor device includes a semiconductor fin formed on an insulator and sidewall spacers formed adjacent the sides of the fin. A gate material layer is formed over the fin and the sidewall spacers and etched to form a gate. The presence of the sidewall spacers causes a topology of the gate material layer to smoothly transition over the fin and the first and second sidewall spacers.

Abstract translation: 半导体器件包括形成在绝缘体上的半导体鳍片和邻近翅片侧面形成的侧壁间隔物。 栅极材料层形成在鳍片和侧壁间隔物上并被蚀刻以形成栅极。 侧壁间隔物的存在导致栅极材料层的拓扑结构平滑地过渡翅片和第一和第二侧壁间隔物。

公开(公告)号：US07041601B1

公开(公告)日：2006-05-09

申请号：US10653103

申请日：2003-09-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L21/311

CPC classification number: H01L29/7842 ,  H01L29/4908 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of manufacturing a MOSFET type semiconductor device includes forming a fin structure and a dummy gate structure over the fin structure. Sidewall spacers may be formed adjacent the dummy gate structure. The dummy gate structure may be later removed and replaced with a metal layer that is formed at a high temperature (e.g., 600°–700° C.). The cooling of the metal layer induces strain to the fin structure that affects the mobility of the double-gate MOSFET.

Abstract translation: 制造MOSFET型半导体器件的方法包括在鳍结构上形成翅片结构和虚拟栅极结构。 侧壁间隔件可以与伪栅极结构相邻地形成。 可以稍后去除虚拟栅极结构并用在高温（例如600℃-700℃）下形成的金属层代替。 金属层的冷却会引起对鳍结构的应变，从而影响双栅极MOSFET的迁移率。

公开(公告)号：US20060089820A1

公开(公告)日：2006-04-27

申请号：US10973186

申请日：2004-10-25

Applicant: Bin Yu ,  Yong Rui

Inventor： Bin Yu ,  Yong Rui

IPC: G06F11/30 ,  G21C17/00 ,  G06F15/00

CPC classification number: G06Q10/10

Abstract: An event-based system and process for recording and playback of collaborative electronic presentations is presented. The present system and process includes a technique for recording collaborative electronic presentations by capturing and storing the interactions between each participant and presentation data where each interaction event is timestamped and linked to a data file comprising the presentation data. The present system and process also includes a technique for playing back the recorded collaborative electronic presentation, which involves displaying the presentation data in an order it was originally presented and reproducing the recorded interactions between each participant and the displayed presentation data at the same point in the presentation that they were originally performed, based on the aforementioned timestamps.

公开(公告)号：US07019363B1

公开(公告)日：2006-03-28

申请号：US09476961

申请日：2000-01-03

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L29/7835 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/6659 ,  H01L29/66659

Abstract: A method of fabricating an integrated circuit utilizes symmetric source/drain junctions. The process can be utilized for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETS). The drain extension is deeper than the source extension. The source extension is more conductive than the drain extension. The transistor has reduced short channel effects and strong drive current and yet is reliable.

Abstract translation: 一种制造集成电路的方法采用对称的源极/漏极结。 该过程可用于P沟道或N沟道金属氧化物半导体效应晶体管（MOSFET）。 漏极扩展比源扩展更深。 源极延伸比漏极延伸更为导电。 晶体管减少了短沟道效应和强大的驱动电流，而且可靠。