公开(公告)号：US09503114B1

公开(公告)日：2016-11-22

申请号：US14855026

申请日：2015-09-15

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Ramy Mohamed Yousry Ahmed Elsayed Awad ,  Jun Cao

IPC分类号： H03M1/06 ,  H03M1/12 ,  H03M1/36

CPC分类号： H03M1/1245 ,  H03M1/1215

摘要： A multi-lane analog to digital converter (ADC) samples an analog input according to multiple phases of a sampling clock. Ideally, the multiple phases of the sampling clock are non-overlapping. The multi-lane ADC includes one or more reset switches to remove any residual samples that can remain after their conversion from an analog signal domain to a digital signal domain. As a result of this removal, the multiple phases of the sampling clock need not to ideally coincide with one other. Rather, some overlap between the multiple phases of the sampling clock can exist while having digital output samples still accurately represent the analog input.

摘要翻译： 多通道模数转换器（ADC）根据采样时钟的多个相位对模拟输入采样。 理想情况下，采样时钟的多个相位是不重叠的。 多通道ADC包括一个或多个复位开关，以去除在从模拟信号域转换为数字信号域之后可以保留的任何残留样本。 作为这种去除的结果，采样时钟的多个阶段不需要理想地彼此重合。 相反，采样时钟的多个相位之间可能存在一些重叠，同时数字输出采样仍然准确地表示模拟输入。

公开(公告)号：US09413381B2

公开(公告)日：2016-08-09

申请号：US14616566

申请日：2015-02-06

申请人： BROADCOM CORPORATION

发明人： Anand Jitendra Vasani ,  Ali Nazemi ,  Jun Cao ,  Afshin Momtaz

IPC分类号： H03M1/66 ,  H03M1/68 ,  H03M1/00 ,  H03M1/10 ,  H03M1/74

CPC分类号： H03M1/68 ,  H03M1/002 ,  H03M1/068 ,  H03M1/1028 ,  H03M1/1047 ,  H03M1/74 ,  H03M1/80

摘要： A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

摘要翻译： 低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。 每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。 每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。 一个或多个相应阻抗的第二节点耦合到输出节点。

公开(公告)号：US20160036538A1

公开(公告)日：2016-02-04

申请号：US14882980

申请日：2015-10-14

申请人： Broadcom Corporation

发明人： Tamer Ali ,  Jun Cao

IPC分类号： H04B17/21 ,  H04L7/00

CPC分类号： H04B17/21 ,  H03K5/135 ,  H03M1/1023 ,  H03M1/1215 ,  H03M1/1245 ,  H04L7/0012

摘要： A device includes process mitigating timing (PMT) circuitry. The PMT circuitry allows for adjustment of a clock signal while compensating for process variation within the PMT circuitry. The PMT circuitry may include process mitigating buffer (PMB) circuitry. The PMB circuitry may utilize replica circuitry and a calibrated resistance to generate a calibrated bias voltage. The calibrated bias voltage may be used to drive component buffer circuits to create a calibrated current response. The calibrated current response may correspond to a selected output impedance for the component buffer circuits. The select output impedance may be used in concert with a variable capacitance to adjust a clock signal in manner that is independent of the process variation within the PMT circuitry.

摘要翻译： 一种设备包括进程减轻时序（PMT）电路。 PMT电路允许调整时钟信号，同时补偿PMT电路内的过程变化。 PMT电路可以包括过程减缓缓冲器（PMB）电路。 PMB电路可以利用复制电路和经校准的电阻来产生校准偏置电压。 校准的偏置电压可用于驱动元件缓冲器电路以产生校准的电流响应。 校准的电流响应可以对应于组件缓冲器电路的选择的输出阻抗。 选择输出阻抗可以与可变电容一起使用，以独立于PMT电路内的过程变化的方式调整时钟信号。

公开(公告)号：US09231571B2

公开(公告)日：2016-01-05

申请号：US14080733

申请日：2013-11-14

申请人： Broadcom Corporation

发明人： Bharath Raghavan ,  Jun Cao ,  Afshin Momtaz

IPC分类号： H04J3/04 ,  H03K5/07 ,  H03M9/00 ,  H04L7/02 ,  H03K5/00 ,  H04L7/00 ,  H04L7/027 ,  H04L7/033

CPC分类号： H03K5/07 ,  H03K2005/00071 ,  H03K2005/00208 ,  H03M9/00 ,  H04L7/0079 ,  H04L7/02 ,  H04L7/027 ,  H04L7/033

摘要： A programmable frequency receiver includes a slicer for receiving data at a first frequency, a de-multiplexer for de-multiplexing the data at a second frequency, a programmable clock generator for generating a clock at the first frequency, and first and second resonant clock amplifiers for amplifying clock signals at the first and second frequencies. The resonant clock amplifiers include an inductor having a low Q value, allowing them to amplify clock signals over the programmable frequency range of the receiver. The second resonant clock amplifier includes digitally tunable delay elements to delay and center the amplified clock signal of the second frequency in the data window at the interface between the slicer and the de-multiplexer. The delay elements can be capacitors. A calibration circuit adjusts capacitive elements within a master clock generator to generate a master clock at the first frequency.

公开(公告)号：US20150035563A1

公开(公告)日：2015-02-05

申请号：US14025058

申请日：2013-09-12

申请人： Broadcom Corporation

发明人： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC分类号： H03K19/0185

CPC分类号： H03K19/018507

摘要： A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

摘要翻译： 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US20150008982A1

公开(公告)日：2015-01-08

申请号：US14042274

申请日：2013-09-30

申请人： Broadcom Corporation

发明人： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC分类号： H03F1/32

CPC分类号： H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

摘要： Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

摘要翻译： 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。

公开(公告)号：US08873606B2

公开(公告)日：2014-10-28

申请号：US13671340

申请日：2012-11-07

申请人： Broadcom Corporation

发明人： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC分类号： H04B1/38 ,  H03D3/02

CPC分类号： H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

摘要： Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

摘要翻译： 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US08791742B2

公开(公告)日：2014-07-29

申请号：US13622223

申请日：2012-09-18

申请人： Broadcom Corporation

发明人： Adesh Garg ,  Jun Cao

IPC分类号： G06F1/04

CPC分类号： H03K5/135 ,  G06F1/10

摘要： A clock driver includes a clock interconnect running to multiple lanes of an integrated circuit chip, the interconnect including a positive clock line and a negative clock line. A clock generator generates a clock signal and a source inductor, through which the clock generator draws DC power, helps drive the clock signal down the interconnect. The source inductor may be tunable. A distributed (or tunable) inductor is connected to and positioned along the positive and negative clock lines between the source inductor and an end of the interconnect. Multiple distributed inductors may be positioned and optionally tuned such as to create a resonant response in the clock signal with substantially similar quality and amplitude as delivered to the multiple lanes. Any of the distributed and source inductors may be switchable to change inductance of the distributed inductors and thus change the clock frequency in the lanes for different communication standards.

摘要翻译： 时钟驱动器包括运行到集成电路芯片的多个通道的时钟互连，该互连包括正时钟线和负时钟线。 时钟发生器产生时钟信号和源电感器，时钟发生器通过该电感器吸取直流电源，有助于将时钟信号驱动到互连。 源电感可以是可调谐的。 分布式（或可调谐）电感器连接到源电感器和互连端之间的正和负时钟线并且位于其间。 多个分布式电感器可以被定位并且可选地调谐，以便在时钟信号中产生具有基本相似的质量和幅度的谐振响应，并且输送到多个通道。 任何分布式和源极感应器都可以切换以改变分布式电感器的电感，从而改变不同通信标准的通道中的时钟频率。

公开(公告)号：US20130243072A1

公开(公告)日：2013-09-19

申请号：US13871831

申请日：2013-04-26

申请人： BROADCOM CORPORATION

发明人： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC分类号： H04L27/00

CPC分类号： H04L27/0002 ,  H04B1/0007 ,  H04B1/406

摘要： According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

摘要翻译： 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。