公开(公告)号：US09036956B2

公开(公告)日：2015-05-19

申请号：US13399098

申请日：2012-02-17

申请人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Chun-Hao Tseng ,  Wan-Yu Lee ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/12 ,  G02B6/138 ,  F21V8/00 ,  G02B6/42

CPC分类号： G02B6/12004 ,  G02B6/0083 ,  G02B6/132 ,  G02B6/136 ,  G02B6/138 ,  G02B6/4214 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12121 ,  G02B2006/12176

摘要： A method of fabricating a waveguide device is disclosed. The method includes providing a substrate having an elector-interconnection region and a waveguide region and forming a patterned dielectric layer and a patterned redistribution layer (RDL) over the substrate in the electro-interconnection region. The method also includes bonding the patterned RDL to a vertical-cavity surface-emitting laser (VCSEL) through a bonding stack. A reflecting-mirror trench is formed in the substrate in the waveguide region, and a reflecting layer is formed over a reflecting-mirror region inside the waveguide region. The method further includes forming and patterning a bottom cladding layer in a wave-tunnel region inside the waveguide region and forming and patterning a core layer and a top cladding layer in the waveguide region.

摘要翻译： 公开了一种制造波导器件的方法。 该方法包括提供具有选通互连区域和波导区域的衬底，并且在电互连区域中的衬底上形成图案化电介质层和图案化再分配层（RDL）。 该方法还包括通过结合堆叠将图案化的RDL结合到垂直腔表面发射激光器（VCSEL）。 在波导区域的基板上形成反射镜沟槽，反射层形成在波导区域内的反射镜区域的上方。 该方法还包括在波导区域内的波通道区域中形成和图案化底包层，并且在波导区域中形成和图案化芯层和顶包层。

公开(公告)号：US08735278B2

公开(公告)日：2014-05-27

申请号：US13550951

申请日：2012-07-17

申请人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

发明人： Ming Han Lee ,  Hai-Ching Chen ,  Hsiang-Huan Lee ,  Tien-I Bao ,  Chi-Lin Teng

IPC分类号： H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/76834 ,  H01L21/76867 ,  H01L21/76885 ,  H01L21/76897 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure is directed to a method of manufacturing an interconnect structure in which a low-k dielectric layer is formed over a semiconductor substrate followed by formation of a copper or copper alloy layer over the low-k dielectric layer. The copper or copper alloy layer is patterned and etched to form a copper body having recesses, which are then filled with a low-k dielectric material. The method allows for formation of a damascene structures without encountering the various problems presented by non-planar features and by porus low-K dielectric damage.

摘要翻译： 本公开涉及一种制造互连结构的方法，其中在半导体衬底上形成低k电介质层，然后在低k电介质层上形成铜或铜合金层。 铜或铜合金层被图案化和蚀刻以形成具有凹部的铜体，然后填充有低k电介质材料。 该方法允许形成镶嵌结构，而不会遇到由非平面特征和孔隙低K电介质损伤所呈现的各种问题。

公开(公告)号：US10180547B2

公开(公告)日：2019-01-15

申请号：US13403566

申请日：2012-02-23

申请人： Wan-Yu Lee ,  Chun-Hao Tseng ,  Hai-Ching Chen ,  Tien-I Bao

发明人： Wan-Yu Lee ,  Chun-Hao Tseng ,  Hai-Ching Chen ,  Tien-I Bao

IPC分类号： G02B6/42 ,  H01S5/022 ,  H01S5/00

摘要： An optical bench on substrate includes a substrate and a trench formed inside the substrate and having a sloping side. A reflector layer is formed over the sloping side. An optical component is mounted over the substrate. The reflector layer is configured to reflect an electromagnetic wave to or from the optical component.

公开(公告)号：US09224643B2

公开(公告)日：2015-12-29

申请号：US13236264

申请日：2011-09-19

申请人： Chung-Ju Lee ,  Tien-I Bao ,  Ming-Shih Yeh ,  Hai-Ching Chen ,  Shau-Lin Shue

发明人： Chung-Ju Lee ,  Tien-I Bao ,  Ming-Shih Yeh ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L21/00 ,  H01L21/768 ,  H01L23/532 ,  H01L21/3213

CPC分类号： H01L21/76885 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/7682 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.

摘要翻译： 本公开提供了形成互连结构的方法的一个实施例。 该方法包括在基板上形成第一介电材料层; 图案化第一介电材料层以在其中形成多个通孔; 在所述第一介电层和所述基板上形成金属层，其中所述金属层填充在所述多个通孔中; 并且蚀刻金属层，使得第一介电材料层上方的金属层的部分被图案化以形成分别与多个通孔对准的多个金属线。

公开(公告)号：US20130069234A1

公开(公告)日：2013-03-21

申请号：US13236264

申请日：2011-09-19

申请人： Chung-Ju Lee ,  Tien-I Bao ,  Ming-Shih Yeh ,  Hai-Ching Chen ,  Shau-Lin Shue

发明人： Chung-Ju Lee ,  Tien-I Bao ,  Ming-Shih Yeh ,  Hai-Ching Chen ,  Shau-Lin Shue

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/76885 ,  H01L21/32134 ,  H01L21/32136 ,  H01L21/7682 ,  H01L21/76852 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure provides one embodiment of a method to form an interconnect structure. The method includes forming a first dielectric material layer on a substrate; patterning the first dielectric material layer to form a plurality of vias therein; forming a metal layer on the first dielectric layer and the substrate, wherein the metal layer fills in the plurality of vias; and etching the metal layer such that portions of the metal layer above the first dielectric material layer are patterned to form a plurality of metal lines, aligned with plurality of vias, respectively.

摘要翻译： 本公开提供了形成互连结构的方法的一个实施例。 该方法包括在基板上形成第一介电材料层; 图案化第一介电材料层以在其中形成多个通孔; 在所述第一介电层和所述基板上形成金属层，其中所述金属层填充在所述多个通孔中; 并且蚀刻金属层，使得第一介电材料层上方的金属层的部分被图案化以形成分别与多个通孔对准的多个金属线。

公开(公告)号：US09087877B2

公开(公告)日：2015-07-21

申请号：US11585610

申请日：2006-10-24

申请人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Ting-Yu Shen ,  Keng-Chu Lin ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Jeng ,  Chen-Hua Yu

IPC分类号： H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76831 ,  H01L21/76826

摘要： A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

摘要翻译： 一种用于形成集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，形成至少覆盖开口侧壁的介电阻挡层，进行处理以改善 介电阻挡层的润湿能力，并用导电材料填充开口，其中导电材料与电介质阻挡层接触。

公开(公告)号：US08629056B2

公开(公告)日：2014-01-14

申请号：US13107549

申请日：2011-05-13

申请人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Chung-Chi Ko ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/4763

CPC分类号： H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

摘要： A method for fabricating an integrated circuit comprises forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, and treating the low-k dielectric layer with a gaseous organic chemical to cause a reaction between the low-k dielectric layer and the gaseous organic chemical. The gaseous organic chemical is free from silicon.

摘要翻译： 一种用于制造集成电路的方法包括在半导体衬底上形成低k电介质层，蚀刻低k电介质层以形成开口，并用气体有机化学品处理低k电介质层以引起第 低k电介质层和气态有机化学品。 气态有机化学物质不含硅。

公开(公告)号：US20080171431A1

公开(公告)日：2008-07-17

申请号：US11654427

申请日：2007-01-17

申请人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

发明人： Chen-Hua Yu ,  Yung-Cheng Lu ,  Pei-Ren Jeng ,  Chia-Cheng Chou ,  Keng-Chu Lin ,  Chung-Chi Ko ,  Tien-I Bao ,  Shwang-Ming Jeng

IPC分类号： H01L21/4763

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76835 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

摘要翻译： 提出了双层多孔低介电常数（低k）互连结构及其制造方法。 具有约2.2的有效介电常数的优选实施例包括与前者直接接触的底部沉积介电层和顶部沉积的介电层。 底层和顶层具有相同的原子组成，但是较高的介电常数值k。 底部介电层用作顶部电介质层的蚀刻停止层，并且顶部介电层可以用作CMP停止层。 制造该结构的一个实施方案包括形成具有第一致孔剂含量的底部电介质层和具有较高致孔剂含量的顶部电介质层。 固化过程在底部电介质层中留下比在顶部电介质层中留下的孔密度更低的孔密度，这导致底部电介质层中较高的介电值k。

公开(公告)号：US07314828B2

公开(公告)日：2008-01-01

申请号：US11184589

申请日：2005-07-19

申请人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/4763

CPC分类号： H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

摘要翻译： 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。

公开(公告)号：US20070020952A1

公开(公告)日：2007-01-25

申请号：US11184589

申请日：2005-07-19

申请人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Keng-Chu Lin ,  Chen-Hua Yu ,  Ching-Ya Wang ,  Chia-Cheng Chou ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/02211 ,  H01L21/0206 ,  H01L21/02074 ,  H01L21/02101 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02334 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/312 ,  H01L21/3122 ,  H01L21/31629 ,  H01L21/76801 ,  H01L21/76814 ,  H01L21/76825 ,  H01L21/76834

摘要： A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

摘要翻译： 形成低k电介质层并在低k电介质层中形成结构的方法包括在衬底上沉积低k电介质层，对低k电介质层进行第一次处理，执行后形成工艺 ，并对低k电介质层进行第二处理。 通过第一次处理，低k电介质层的k值降低。 对低k电介质层进行的后期处理包括至少一个低k​​电介质材料破坏过程。 第二种处理恢复了低k电介质层。 优选地，第一和第二处理中的每一个包括选自电子束固化，紫外线固化，等离子体固化，SCCO 2清洁及其组合的固化过程。