公开(公告)号：US6147381A

公开(公告)日：2000-11-14

申请号：US187501

申请日：1998-11-06

申请人： Franz Hirler ,  Frank Pfirsch ,  Wolfgang Werner

发明人： Franz Hirler ,  Frank Pfirsch ,  Wolfgang Werner

IPC分类号： H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/739 ,  H01L29/72

CPC分类号： H01L29/0623 ,  H01L29/0619 ,  H01L29/7395 ,  H01L29/0847

摘要： A field effect-controllable semiconductor component, such as a new IGBT using planar technology, includes a shielding zone disposed about a base zone, resulting in elevation of a minority charge carrier density at a cathode side of the IGBT, leading to a reduction of forward voltage. The effect of a drift field produced due to a concentration gradient between the shielding zone and the base zone is that the inner zone no longer acts as a sink for the minority charge carriers. In order to ensure that the breakdown voltage of the IGBT is not reduced by the incorporation of the shielding zone, a non-connected, floating region of high conductivity is disposed in the region of the inner zone. A lower edge of the non-connected, floating region is deeper in the inner zone than a lower edge of the shielding zone. The non-connected, floating region has a conduction type opposite that of the shielding zone and the inner zone.

摘要翻译： 诸如使用平面技术的新型IGBT的场效应可控半导体部件包括围绕基极区设置的屏蔽区域，导致IGBT的阴极侧的少量电荷载流子密度升高，导致向前的减少 电压。 由于屏蔽区域和基极区域之间的浓度梯度而产生的漂移场的影响是内部区域不再充当少量电荷载流子的吸收器。 为了确保IGBT的击穿电压不被并入屏蔽区域而降低，在内部区域中设置高导电性的非连接浮动区域。 非连接的浮动区域的下边缘在内区域比屏蔽区域的下边缘更深。 非连接的浮动区域具有与屏蔽区域和内部区域相反的导电类型。

公开(公告)号：US5736445A

公开(公告)日：1998-04-07

申请号：US683301

申请日：1996-07-18

申请人： Frank Pfirsch

发明人： Frank Pfirsch

IPC分类号： H01L27/06 ,  H01L21/266 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/092 ,  H01L29/08 ,  H01L29/78

CPC分类号： H01L21/823892 ,  H01L21/266 ,  H01L21/823456 ,  H01L29/0847 ,  H01L29/0873 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66712 ,  H01L29/7802 ,  H01L29/7835

摘要： A method for producing at least two transistors in one semiconductor body includes placing a first well doping region for receiving a first transistor and a second well doping region serving as a charge carrier sink region for a second transistor into a semiconductor body by masked doping with ensuing heat treatment. A mask for forming the second well doping region includes regions being permeable to a dopant and regions being impermeable to the dopant.

摘要翻译： 一种用于在一个半导体器件中制造至少两个晶体管的方法包括：通过掩模掺杂放置用于接收第一晶体管的第一阱掺杂区域和用作第二晶体管的电荷载流子阱区域的第二阱掺杂区域， 热处理。 用于形成第二阱掺杂区域的掩模包括对掺杂剂是可渗透的区域，并且对掺杂剂是不可渗透的区域。

公开(公告)号：US09214521B2

公开(公告)日：2015-12-15

申请号：US13529185

申请日：2012-06-21

申请人： Dorothea Werber ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Carsten Schaeffer ,  Volodymyr Komarnitskyy ,  Anton Mauder

发明人： Dorothea Werber ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Carsten Schaeffer ,  Volodymyr Komarnitskyy ,  Anton Mauder

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/32 ,  H01L29/861 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/167 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/10

CPC分类号： H01L29/32 ,  H01L21/26506 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/402 ,  H01L29/41766 ,  H01L29/423 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/8611

摘要： A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first type, a drift region of the second conductivity type, and a first electrode. The first and second emitter regions are arranged between the drift region and first electrode and each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source and body regions. A parasitic region of the first conductivity type is disposed outside the cell region and includes at least one section with charge carrier lifetime reduction means.

摘要翻译： 半导体器件包括第一导电类型的第一发射极区域，与第一类型互补的第二导电类型的第二发射极区域，第二导电类型的漂移区域和第一电极。 第一和第二发射极区域布置在漂移区域和第一电极之间，并且每个连接到第一电极。 单元区域的器件单元包括邻接漂移区的第一导电类型的主体区域，与身体区域邻接的第二导电类型的源极区域和与身体区域相邻并且与身体区域电介质绝缘的栅电极， 栅极电介质。 第二电极电连接到源区和体区。 第一导电类型的寄生区域设置在单元区域的外部，并且包括至少一个带有载流子寿命减少装置的区段。

公开(公告)号：US09012311B2

公开(公告)日：2015-04-21

申请号：US12170470

申请日：2008-07-10

申请人： Frank Pfirsch ,  Hans-Joachim Schulze

发明人： Frank Pfirsch ,  Hans-Joachim Schulze

IPC分类号： H01L21/425 ,  H01L29/167 ,  H01L21/22 ,  H01L21/265 ,  H01L29/06 ,  H01L29/08 ,  H01L29/36 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861

CPC分类号： H01L29/0623 ,  H01L21/221 ,  H01L21/26506 ,  H01L29/0634 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/167 ,  H01L29/36 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7811 ,  H01L29/861 ,  H01L29/8611

摘要： In a method for producing a semiconductor body, impurities which act as recombination centers in the semiconductor body and form a recombination zone are introduced into the semiconductor body during the process of producing the semiconductor body. In a semiconductor component, comprising a semiconductor body having a front surface and an opposite rear surface, and also a recombination zone formed by impurities between the front and rear surfaces, wherein the impurities act as recombination centers, the surface state density at the front and rear surfaces of the semiconductor body is just as high as the surface state density at a front and rear surface of an identical semiconductor body without a recombination zone.

摘要翻译： 在制造半导体体的方法中，在制造半导体体的过程中，在半导体本体中作为复合中心并形成复合区的杂质被引入半导体本体。 在半导体元件中，包括具有前表面和相对后表面的半导体本体，以及由前表面和后表面之间的杂质形成的复合区，其中杂质作为复合中心，前面的表面状态密度和 半导体本体的后表面与没有复合区的同一半导体主体的前表面和后表面的表面状态密度一样高。

公开(公告)号：US20130264607A1

公开(公告)日：2013-10-10

申请号：US13441364

申请日：2012-04-06

申请人： Dorothea Werber ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Franz Hirler ,  Alexander Philippou

发明人： Dorothea Werber ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze ,  Franz Hirler ,  Alexander Philippou

IPC分类号： H01L29/739

CPC分类号： H01L29/7396 ,  H01L29/0696 ,  H01L29/0834

摘要： A semiconductor includes a drift zone of a first conductivity type arranged between a first side and a second side of a semiconductor body. The semiconductor device further includes a first region of the first conductivity type and a second region of a second conductivity type subsequently arranged along a first direction parallel to the second side. The semiconductor device further includes an electrode at the second side adjoining the first and second regions. The semiconductor device further includes a third region of the second conductivity type arranged between the drift zone and the first region. The third region is spaced apart from the second region and from the second side.

摘要翻译： 半导体包括布置在半导体主体的第一侧和第二侧之间的第一导电类型的漂移区。 半导体器件还包括第一导电类型的第一区域和沿着平行于第二侧面的第一方向布置的第二导电类型的第二区域。 半导体器件还包括邻近第一和第二区域的第二侧的电极。 半导体器件还包括布置在漂移区和第一区之间的第二导电类型的第三区。 第三区域与第二区域和第二区域隔开。

公开(公告)号：US20130140616A1

公开(公告)日：2013-06-06

申请号：US13312180

申请日：2011-12-06

申请人： Hans-Joachim Schulze ,  Anton Mauder ,  Frank Pfirsch

发明人： Hans-Joachim Schulze ,  Anton Mauder ,  Frank Pfirsch

IPC分类号： H01L27/06

CPC分类号： H01L23/62 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/088 ,  H01L29/0696 ,  H01L29/41766 ,  H01L29/42364 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment of an integrated circuit, the integrated circuit includes a power transistor with a power control terminal, a first power load terminal and a second power load terminal. The integrated circuit further includes an auxiliary transistor with an auxiliary control terminal, a first auxiliary load terminal and a second auxiliary load terminal. The first auxiliary load terminal is electrically coupled to the power control terminal. The integrated circuit further includes a capacitor with a first capacitor electrode, a second capacitor electrode and a capacitor dielectric layer. The capacitor dielectric layer includes at least one of a ferroelectric material and a paraelectric material. The first capacitor electrode is electrically coupled to the auxiliary control terminal.

摘要翻译： 在集成电路的一个实施例中，集成电路包括具有功率控制端子的功率晶体管，第一功率负载端子和第二功率负载端子。 集成电路还包括具有辅助控制端子的辅助晶体管，第一辅助负载端子和第二辅助负载端子。 第一辅助负载端子电耦合到功率控制端子。 集成电路还包括具有第一电容器电极，第二电容器电极和电容器电介质层的电容器。 电容介质层包括铁电材料和顺电材料中的至少一种。 第一电容器电极电耦合到辅助控制端子。

公开(公告)号：US08435853B2

公开(公告)日：2013-05-07

申请号：US12871038

申请日：2010-08-30

申请人： Franz Hirler ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze

发明人： Franz Hirler ,  Anton Mauder ,  Frank Pfirsch ,  Hans-Joachim Schulze

IPC分类号： H01L21/8234

CPC分类号： H01L29/66143 ,  H01L21/823487 ,  H01L29/0626 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/6609 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7803 ,  H01L29/7804 ,  H01L29/7808 ,  H01L29/7813

摘要： A method for forming a field effect power semiconductor is provided. The method includes providing a semiconductor body, a conductive region arranged next to a main surface of the semiconductor body, and an insulating layer arranged on the main horizontal surface. A narrow trench is etched through the insulating layer to expose the conductive region. A polycrystalline semiconductor layer is deposited and a vertical poly-diode structure is formed. The polycrystalline semiconductor layer has a minimum vertical thickness of at least half of the maximum horizontal extension of the narrow trench. A polycrystalline region which forms at least a part of a vertical poly-diode structure is formed in the narrow trench by maskless back-etching of the polycrystalline semiconductor layer. Further, a semiconductor device with a trench poly-diode is provided.

摘要翻译： 提供了一种用于形成场效应功率半导体的方法。 该方法包括提供半导体本体，邻近半导体主体的主表面布置的导电区域和布置在主水平表面上的绝缘层。 通过绝缘层蚀刻窄沟槽以暴露导电区域。 沉积多晶半导体层并形成垂直多晶二极管结构。 多晶半导体层的最小垂直厚度为窄沟槽的最大水平延伸的至少一半。 通过多晶半导体层的无掩模背面蚀刻，在窄沟槽中形成形成垂直多晶二极管结构的至少一部分的多晶区域。 此外，提供了具有沟槽多晶二极管的半导体器件。

公开(公告)号：US08384151B2

公开(公告)日：2013-02-26

申请号：US13007902

申请日：2011-01-17

申请人： Frank Pfirsch

发明人： Frank Pfirsch

IPC分类号： H01L29/66

CPC分类号： H01L29/7395 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/7397 ,  H01L29/7802 ,  H01L29/7813

摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor body with a base region and a first electrode arranged on a main horizontal surface of the semiconductor body. The semiconductor body further includes an IGBT-cell with a body region forming a first pn-junction with the base region, and a diode-cell with an anode region forming a second pn-junction with the base region. A source region in ohmic contact with the first electrode and an anti-latch-up region in ohmic contact with the first electrode are, in a vertical cross-section, only formed in the IGBT-cell. The anti-latch-up region has higher maximum doping concentration than the body region. Further a reverse conducting IGBT is provided.

摘要翻译： 提供半导体器件。 半导体器件包括具有基极区域的半导体本体和布置在半导体本体的主水平表面上的第一电极。 半导体本体还包括具有与基极区形成第一pn结的主体区域的IGBT单元和具有与基极区域形成第二pn结的阳极区域的二极管单元。 与第一电极欧姆接触的源极区域和与第一电极欧姆接触的防闩锁区域在垂直截面中仅形成在IGBT电池中。 抗闩锁​​区域具有比身体区域更高的最大掺杂浓度。 此外，提供反向导通IGBT。

公开(公告)号：US20120313225A1

公开(公告)日：2012-12-13

申请号：US13564158

申请日：2012-08-01

申请人： Frank Pfirsch ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide

发明人： Frank Pfirsch ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide

IPC分类号： H01L21/66 ,  H01L29/36

CPC分类号： H01L29/7802 ,  H01L21/263 ,  H01L21/266 ,  H01L21/322 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712

摘要： An integrated circuit and method for making an integrated circuit including doping a semiconductor body is disclosed. One embodiment provides defect-correlated donors and/or acceptors. The defects required for this are produced by electron irradiation of the semiconductor body. Form defect-correlated donors and/or acceptors with elements or element compounds are introduced into the semiconductor body.

摘要翻译： 公开了一种用于制造包括掺杂半导体本体的集成电路的集成电路和方法。 一个实施例提供缺陷相关的供体和/或受体。 所需的缺陷是通过半导体本体的电子照射产生的。 具有元素或元素化合物的形式缺陷相关的供体和/或受体被引入半导体体。

公开(公告)号：US08264040B2

公开(公告)日：2012-09-11

申请号：US11653089

申请日：2007-01-12

申请人： Frank Pfirsch

发明人： Frank Pfirsch

IPC分类号： H01L29/66

CPC分类号： H01L29/7825 ,  H01L29/0634 ,  H01L29/0657 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66325 ,  H01L29/66348 ,  H01L29/66681 ,  H01L29/66704 ,  H01L29/7393 ,  H01L29/7816

摘要： A power transistor includes a semiconductor layer an electrode layer. The semiconductor layer having a source zone, a drain zone spaced apart from the source zone in a lateral direction, a drift zone adjacent to the drain zone, and a body zone. The body zone is interposed between the drift zone and the source zone. The electrode layer is dielectrically insulated from the semiconductor layer, and includes a gate electrode divided into at least two sections and a field plate. The field plate is arranged at a first height level relative to the semiconductor layer. A first gate electrode section is arranged at least partially at a second height level, which is lower than the first height level relative to the semiconductor layer. A second gate electrode section, which is laterally displaced from the first gate electrode section, is disposed at a first intermediate level arranged between the first and second height levels.

摘要翻译： 功率晶体管包括半导体层和电极层。 所述半导体层具有源极区域，在横向方向上与所述源极区域隔开的漏极区域，与所述排出区域相邻的漂移区域以及主体区域。 体区位于漂移区和源区之间。 电极层与半导体层介电绝缘，并且包括划分为至少两个部分的栅电极和场板。 场板相对于半导体层布置在第一高度水平。 第一栅极电极部分至少部分地布置在相对于半导体层低于第一高度水平的第二高度水平处。 从第一栅极电极部分横向移位的第二栅极电极部分设置在布置在第一和第二高度电平之间的第一中间电平处。