公开(公告)号：US20080265256A1

公开(公告)日：2008-10-30

申请号：US11796369

申请日：2007-04-27

Applicant: Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

Inventor： Chun-Chieh Lin ,  Wei-Hua Hsu ,  Yu-En Percy Chang ,  Chung Li Chang ,  Chi-Feng Cheng ,  Win Hung ,  Kishimoto Ko

IPC: H01L29/94

CPC classification number: H01L29/665 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7848

Abstract: A semiconductor structure and methods for forming the same are provided. The semiconductor structure includes a semiconductor substrate; a gate stack on the semiconductor substrate; a SiGe region in the semiconductor substrate and adjacent the gate stack, wherein the SiGe region has a first atomic percentage of germanium to germanium and silicon; and a silicide region over the SiGe region. The silicide region has a second atomic percentage of germanium to germanium and silicon. The second atomic percentage is substantially lower than the first atomic percentage.

Abstract translation: 提供半导体结构及其形成方法。 半导体结构包括半导体衬底; 半导体衬底上的栅极堆叠; SiGe区域，其中SiGe区域具有锗到锗和硅的第一原子百分比; 以及SiGe区域上的硅化物区域。 硅化物区域具有锗与锗和硅的第二原子百分比。 第二原子百分比基本上低于第一原子百分数。

公开(公告)号：US07423347B2

公开(公告)日：2008-09-09

申请号：US11334849

申请日：2006-01-19

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract translation: 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US07381604B2

公开(公告)日：2008-06-03

申请号：US11423457

申请日：2006-06-12

Applicant: Chun-Chieh Lin ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Yee-Chia Yeo

IPC: H01L21/336

CPC classification number: H01L21/823425 ,  H01L21/76224 ,  H01L21/823412 ,  H01L29/165 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7848

Abstract: A strained-channel semiconductor structure and method of fabricating the same. The strained-channel semiconductor structure comprises a substrate composed of a first semiconductor material with a first natural lattice constant. A channel region is disposed in the substrate and a gate stack is disposed over the strained channel region. A pair of source/drain regions are oppositely disposed in the substrate adjacent to the channel region, wherein each of the source/drain regions comprises a lattice-mismatched zone comprising a second semiconductor material with a second natural lattice constant rather than the first natural lattice constant, an inner side and an outer side corresponding to the gate stack, and at least one outer sides laterally contacts the first semiconductor material of the substrate.

Abstract translation: 应变通道半导体结构及其制造方法。 应变通道半导体结构包括由具有第一自然晶格常数的第一半导体材料构成的衬底。 通道区域设置在衬底中，并且栅堆叠设置在应变通道区域上。 一对源极/漏极区域相邻地设置在衬底中，与沟道区域相邻，其中源极/漏极区域中的每个源极/漏极区域包括具有第二自然晶格常数而不是第一自然晶格的第二半导体材料的晶格失配区域 常数，对应于栅极叠层的内侧和外侧，并且至少一个外侧横向接触基板的第一半导体材料。

公开(公告)号：US20070164439A1

公开(公告)日：2007-07-19

申请号：US11334849

申请日：2006-01-19

Applicant: Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

Inventor： Chung-Hsien Chen ,  Chun-Chieh Lin ,  Minghsing Tsai ,  Shau-Lin Shue

IPC: H01L23/48

CPC classification number: H01L23/53238 ,  H01L21/2885 ,  H01L21/76877 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor interconnect structure having reduced hillock formation and a method for forming the same are provided. The semiconductor interconnect structure includes a conductor formed in a dielectric layer. The conductor includes at least three sub-layers, wherein the ratio of the impurity concentrations in neighboring sub-layers is preferably greater than about two.

Abstract translation: 提供了具有减小的小丘形成的半导体互连结构及其形成方法。 半导体互连结构包括形成在电介质层中的导体。 导体包括至少三个子层，其中相邻子层中杂质浓度的比优选大于约2。

公开(公告)号：US07235838B2

公开(公告)日：2007-06-26

申请号：US10881372

申请日：2004-06-30

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee

IPC: H01L27/108

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/10832 ,  H01L27/10835 ,  H01L27/10858 ,  H01L27/10861 ,  H01L27/1203 ,  H01L28/55 ,  H01L28/82

Abstract: A method for forming a semiconductor device including a DRAM cell structure comprising a silicon on insulator (SOI) substrate with an embedded capacitor structure including providing a substrate comprising an overlying first electrically insulating layer; forming a first electrically conductive layer on the first electrically insulating layer to form a first electrode; forming a capacitor dielectric layer on the first electrode; forming a second electrically conductive layer on the capacitor dielectric layer to form a second electrode; forming a second electrically insulating layer on the second electrode; and, forming a monocrystalline silicon layer over the second electrode to form an SOI substrate comprising a first capacitor structure.

Abstract translation: 一种用于形成半导体器件的方法，该半导体器件包括具有嵌入式电容器结构的绝缘体上硅（SOI）衬底的DRAM单元结构，包括提供包括上覆的第一电绝缘层的衬底; 在所述第一电绝缘层上形成第一导电层以形成第一电极; 在所述第一电极上形成电容器电介质层; 在所述电容器介电层上形成第二导电层以形成第二电极; 在所述第二电极上形成第二电绝缘层; 以及在所述第二电极上形成单晶硅层以形成包括第一电容器结构的SOI衬底。

公开(公告)号：US07175709B2

公开(公告)日：2007-02-13

申请号：US10847099

申请日：2004-05-17

Applicant: Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

Inventor： Pang-Yen Tsai ,  Liang-Gi Yao ,  Chun-Chieh Lin ,  Wen-Chin Lee ,  Shih-Chang Chen

IPC: C30B25/04

CPC classification number: C30B25/00 ,  C30B29/06 ,  C30B29/52 ,  Y10S438/933

Abstract: A method of forming an epitaxial layer of uniform thickness is provided to improve surface flatness. A substrate is first provided and a Si base layer is then formed on the substrate by epitaxy. A Si—Ge layer containing 5 to 10% germanium is formed on the Si base layer by epitaxy to normalize the overall thickness of the Si base layer and the Si—Ge layer containing 5 to 10% germanium.

Abstract translation: 提供了形成均匀厚度的外延层的方法以改善表面平坦度。 首先提供衬底，然后通过外延在衬底上形成Si基层。 通过外延在Si基底层上形成含有5〜10％锗的Si-Ge层，以使Si基层和含有5〜10％锗的Si-Ge层的整体厚度归一化。

公开(公告)号：US06963114B2

公开(公告)日：2005-11-08

申请号：US10749273

申请日：2003-12-29

Applicant: Chun-Chieh Lin

Inventor： Chun-Chieh Lin

IPC: H01L29/41 ,  H01L21/02 ,  H01L21/336 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/785 ,  H01L27/1203 ,  H01L29/41791 ,  H01L29/42384 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/66795 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectronic device including an insulator located over a substrate, a semiconductor feature and a contact layer. The semiconductor feature has a thickness over the insulator, a first surface opposite the insulator, and a sidewall spanning at least a portion of the thickness. The contact layer has a first member extending over at least a portion of the first surface and a second member spanning at least a portion of the sidewall.

Abstract translation: 包括位于衬底上的绝缘体，半导体特征和接触层的微电子器件。 半导体特征具有超过绝缘体的厚度，与绝缘体相对的第一表面和横跨至少一部分厚度的侧壁。 接触层具有在第一表面的至少一部分上延伸的第一构件和跨越侧壁的至少一部分的第二构件。

公开(公告)号：US20050158923A1

公开(公告)日：2005-07-21

申请号：US11081104

申请日：2005-03-15

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo

IPC: H01L21/336 ,  H01L21/84 ,  H01L27/01 ,  H01L29/45 ,  H01L29/68 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/78618 ,  H01L29/78654

Abstract: A semiconductor device (100), including a dielectric pedestal (220) located above and integral to a substrate (110) and having first sidewalls (230), a channel region (210) located above the dielectric pedestal (220) and having second sidewalls (240), and source and drain regions (410) opposing the channel region (210) and each substantially spanning one of the second sidewalls (240). An integrated circuit (800) incorporating the semiconductor device (100) is also disclosed, as well as a method of manufacturing the semiconductor device (100).

Abstract translation: 一种半导体器件（100），包括位于衬底（110）上方并与衬底（110）成一体并具有第一侧壁（230）的电介质基座（220），位于电介质基座（220）上方的通道区域（210） （240），以及与沟道区（210）相对并且每个基本跨越第二侧壁（240）中的一个的源极和漏极区（410）。 还公开了结合半导体器件（100）的集成电路（800），以及制造半导体器件（100）的方法。

公开(公告)号：US20050127400A1

公开(公告)日：2005-06-16

申请号：US10745831

申请日：2003-12-24

Applicant: Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ke ,  Chun-Chieh Lin ,  Chenming Hu

Inventor： Yee-Chia Yeo ,  Wen-Chin Lee ,  Chih-Hsin Ko ,  Chung-Hu Ke ,  Chun-Chieh Lin ,  Chenming Hu

IPC: H01L27/06 ,  H01L29/02 ,  H01L29/165 ,  H01L29/8605 ,  H01L31/109

CPC classification number: H01L27/0629 ,  H01L29/165 ,  H01L29/8605

Abstract: A heterostructure resistor comprises a doped region formed in a portion of a semiconductor substrate, the substrate comprising a first semiconductor material having a first natural lattice constant. The doped region comprises a semiconductor layer overlying the semiconductor substrate. The semiconductor layer comprises a second semiconductor material with a second natural lattice constant.

Abstract translation: 异质结构电阻器包括形成在半导体衬底的一部分中的掺杂区域，该衬底包括具有第一自然晶格常数的第一半导体材料。 掺杂区域包括覆盖半导体衬底的半导体层。 半导体层包括具有第二自然晶格常数的第二半导体材料。

公开(公告)号：US20050045965A1

公开(公告)日：2005-03-03

申请号：US10831021

申请日：2004-04-23

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/43 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。