公开(公告)号：US20050110144A1

公开(公告)日：2005-05-26

申请号：US10707117

申请日：2003-11-21

申请人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

发明人： Cyril Cabral ,  Steffen Kaldor ,  Hyungjun Kim ,  Stephen Rossnagel

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC分类号： H01L21/76843 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： In an interconnect structure of an integrated circuit, a diffusion barrier film in a damascene structure is formed of a film having the composition TaNx, where x is greater than 1.2 and with a thickness of 0.5 to 5 nm.

摘要翻译： 在集成电路的互连结构中，镶嵌结构中的扩散阻挡膜由具有组成TaN x x的膜形成，其中x大于1.2，厚度为0.5至5nm 。

公开(公告)号：US20050070098A1

公开(公告)日：2005-03-31

申请号：US10674645

申请日：2003-09-30

申请人： John Bruley ,  Cyril Cabral ,  Christian Lavoie ,  Tina Wagner ,  Yun Wang ,  Horatl Wlldman ,  Wong Hon

发明人： John Bruley ,  Cyril Cabral ,  Christian Lavoie ,  Tina Wagner ,  Yun Wang ,  Horatl Wlldman ,  Wong Hon

IPC分类号： H01L21/336 ,  H01L21/44 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76843 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/76855 ,  H01L21/76856 ,  H01L29/665

摘要： The present invention provides a method for forming an interconnect to a cobalt or nickel silicide having a TiN diffusion barrier. The inventive method comprises providing an initial structure having vias to exposed silicide regions positioned on a substrate; annealing the initial structure in a nitrogen-containing ambient, wherein a nitrogen passivation layer is formed atop the exposed silicide region; depositing Ti atop the nitrogen passivation layer; annealing the Ti in a nitrogen-containing ambient to form a TiN diffusion barrier and an amorphous Ti cobalt silicide between the TiN diffusion layer and the cobalt or nickel silicide and depositing an interconnect metal within the vias and atop the TiN diffusion barrier. The nitrogen passivation layer substantially restricts diffusion between the Ti and silicide layers minimizing the amorphous Ti cobalt silicide layer that forms. Therefore, the amorphous Ti cobalt or Ti nickel silicide is restricted to a thickness of less than about 3.0 nm.

摘要翻译： 本发明提供一种用于形成具有TiN扩散阻挡层的钴或镍硅化物的互连的方法。 本发明的方法包括提供具有通孔的初始结构，以暴露出位于基板上的硅化物区域; 在含氮环境中退火初始结构，其中在暴露的硅化物区域上形成氮钝化层; 在氮钝化层顶上沉积Ti; 在含氮环境中退火Ti以在TiN扩散层和钴或镍硅化物之间形成TiN扩散阻挡层和非晶Ti钴硅化物，并在通孔内和TiN扩散势垒顶上沉积互连金属。 氮钝化层基本上限制了Ti和硅化物层之间的扩散，使形成的无定形Ti钴硅化物层最小化。 因此，非晶Ti钴或Ti镍硅化物被限制在小于约3.0nm的厚度。

公开(公告)号：US20080220606A1

公开(公告)日：2008-09-11

申请号：US12107992

申请日：2008-04-23

申请人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

发明人： Cyril Cabral ,  Roy A. Carruthers ,  Christophe Detavernier ,  Simon Gaudet ,  Christian Lavoie ,  Huiling Shang

IPC分类号： H01L21/28

CPC分类号： H01L21/28525 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665

摘要： A method for forming germano-silicide contacts atop a Ge-containing layer that is more resistant to etching than are conventional silicide contacts that are formed from a pure metal is provided. The method of the present invention includes first providing a structure which comprises a plurality of gate regions located atop a Ge-containing substrate having source/drain regions therein. After this step of the present invention, a Si-containing metal layer is formed atop the said Ge-containing substrate. In areas that are exposed, the Ge-containing substrate is in contact with the Si-containing metal layer. Annealing is then performed to form a germano-silicide compound in the regions in which the Si-containing metal layer and the Ge-containing substrate are in contact; and thereafter, any unreacted Si-containing metal layer is removed from the structure using a selective etch process. In some embodiments, an additional annealing step can follow the removal step. The method of the present invention provides a structure having a germano-silicide contact layer atop a Ge-containing substrate, wherein the germano-silicide contact layer contains more Si than the underlying Ge-containing substrate.

摘要翻译： 提供了一种形成锗硅化物的方法，该方法与由纯金属形成的常规硅化物接触相比更能抵抗蚀刻的含Ge层顶部接触。 本发明的方法包括首先提供一种结构，该结构包括位于其中具有源极/漏极区域的含Ge衬底顶部的多个栅极区域。 在本发明的该步骤之后，在所述含Ge基材上形成含Si金属层。 在暴露的区域中，含Ge衬底与含Si金属层接触。 然后进行退火以在含Si金属层和含Ge基板接触的区域中形成锗化硅化合物; 此后，使用选择性蚀刻工艺从结构中除去任何未反应的含Si金属层。 在一些实施方案中，附加的退火步骤可以跟随去除步骤。 本发明的方法提供了一种在含Ge衬底顶上具有锗硅化物接触层的结构，其中锗硅化物接触层含有比下面的含Ge衬底更多的Si。

公开(公告)号：US20070249131A1

公开(公告)日：2007-10-25

申请号：US11408522

申请日：2006-04-21

申请人： Scott Allen ,  Cyril Cabral ,  Kevin Dezfulian ,  Sunfei Fang ,  Brian Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement Wann ,  Huilong Zhu

发明人： Scott Allen ,  Cyril Cabral ,  Kevin Dezfulian ,  Sunfei Fang ,  Brian Greene ,  Rajarao Jammy ,  Christian Lavoie ,  Zhijiong Luo ,  Hung Ng ,  Chun-Yung Sung ,  Clement Wann ,  Huilong Zhu

IPC分类号： H01L21/336 ,  H01L21/44

CPC分类号： H01L21/268 ,  H01L21/2686 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/324 ,  H01L29/517 ,  H01L29/665

摘要： An opto-thermal annealing method for forming a field effect transistor uses a reflective metal gate so that electrical properties of the metal gate and also interface between the metal gate and a gate dielectric are not compromised when opto-thermal annealing a source/drain region adjacent the metal gate. Another opto-thermal annealing method may be used for simultaneously opto-thermally annealing: (1) a silicon layer and a silicide forming metal layer to form a fully silicided gate; and (2) a source/drain region to form an annealed source/drain region. An additional opto-thermal annealing method may use a thermal insulator layer in conjunction with a thermal absorber layer to selectively opto-thermally anneal a silicon layer and a silicide forming metal layer to form a fully silicide gate.

摘要翻译： 用于形成场效应晶体管的光热退火方法使用反射金属栅极，使得当相邻的源极/漏极区域进行光热退火时，金属栅极的电特性以及金属栅极和栅极电介质之间的界面不受损害 金属门。 另一种光热退火方法可以用于同时光热退火：（1）硅层和形成硅化物的金属层以形成完全硅化的栅极; 和（2）源/漏区以形成退火的源/漏区。 附加的光热退火方法可以使用与热吸收层结合的热绝缘体层来选择性地使硅层和形成硅化物的金属层光退火以形成完全硅化物栅极。

公开(公告)号：US20060186490A1

公开(公告)日：2006-08-24

申请号：US11372140

申请日：2006-03-10

申请人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

发明人： Cyril Cabral ,  Christophe Detavernier ,  Rajarao Jammy ,  Katherine Saenger

IPC分类号： H01L29/94 ,  H01L29/76

CPC分类号： H01L29/4966 ,  H01L21/823842

摘要： A semiconductor device such as a complementary metal oxide semiconductor (CMOS) comprising at least one FET that comprises a gate electrode comprising a metal carbide and method of fabrication are provided. The CMOS comprises dual work function metal gate electrodes whereby the dual work functions are provided by a metal and a carbide of a metal.

公开(公告)号：US20060121665A1

公开(公告)日：2006-06-08

申请号：US11254934

申请日：2005-10-20

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

摘要翻译： 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在用于容纳第一类型半导体器件的半导体衬底中形成第一阱区; 在所述半导体衬底中形成用于容纳第二类型半导体器件的第二阱区; 用掩模屏蔽第一类型半导体器件; 在所述第二类型半导体器件上沉积第一金属层; 在所述第二类型半导体器件上执行第一自对准硅化物形成; 去除面膜; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及在所述第一类型半导体器件上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同硅化物材料的工艺。

公开(公告)号：US20060121663A1

公开(公告)日：2006-06-08

申请号：US10904885

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  Christian Lavoie ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  Christian Lavoie ,  Clement Wann

IPC分类号： H01L21/8238

CPC分类号： H01L21/823835

摘要： A method of forming a dual self-aligned fully silicided gate in a CMOS device requiring only one lithography level, wherein the method comprises forming a first type semiconductor device having a first well region in a semiconductor substrate, first source/drain silicide areas in the first well region, and a first type gate isolated from the first source/drain silicide areas; forming a second type semiconductor device having a second well region in the semiconductor substrate, second source/drain silicide areas in the second well region, and a second type gate isolated from the second source/drain silicide areas; selectively forming a first metal layer over the second type semiconductor device; performing a first fully silicided (FUSI) gate formation on only the second type gate; depositing a second metal layer over the first and second type semiconductor devices; and performing a second FUSI gate formation on only the first type gate.

摘要翻译： 一种在仅需要一个光刻级别的CMOS器件中形成双自对准全硅化栅的方法，其中所述方法包括在半导体衬底中形成具有第一阱区的第一类型半导体器件，其中第一源极/漏极硅化物区域 第一阱区域和从第一源极/漏极硅化物区域隔离的第一类型栅极; 形成在所述半导体衬底中具有第二阱区域的第二类型半导体器件，所述第二阱区域中的第二源极/漏极硅化物区域和与所述第二源极/漏极硅化物区域隔离的第二类型栅极; 在所述第二类型半导体器件上选择性地形成第一金属层; 仅在第二型栅极上执行第一完全硅化（FUSI）栅极形成; 在所述第一和第二类型半导体器件上沉积第二金属层; 以及仅在第一类型栅极上执行第二FUSI栅极形成。

公开(公告)号：US20060040439A1

公开(公告)日：2006-02-23

申请号：US11203952

申请日：2005-08-15

申请人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

发明人： Dae-Gyu Park ,  Cyril Cabral ,  Oleg Gluschenkov ,  Hyungjun Kim

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823857 ,  Y10S257/90 ,  Y10S438/942

摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.

公开(公告)号：US20050269634A1

公开(公告)日：2005-12-08

申请号：US10863830

申请日：2004-06-04

申请人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Nestor Bojarczuk ,  Cyril Cabral ,  Eduard Cartier ,  Matthew Copel ,  Martin Frank ,  Evgeni Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20050176247A1

公开(公告)日：2005-08-11

申请号：US11075289

申请日：2005-03-08

申请人： Cyril Cabral ,  Roy Carruthers ,  Christophe Detavernier ,  James Harper ,  Christian Lavoie

发明人： Cyril Cabral ,  Roy Carruthers ,  Christophe Detavernier ,  James Harper ,  Christian Lavoie

IPC分类号： C04B35/58 ,  C22F1/00 ,  C23C10/00 ,  H01L21/283 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/44 ,  H01L21/60 ,  H01L21/768

CPC分类号： C04B35/58 ,  C04B35/58085 ,  C04B2235/40 ,  C04B2235/404 ,  C04B2235/405 ,  C04B2235/408 ,  C23C26/00 ,  C23C30/00 ,  H01L21/28518 ,  H01L21/76889

摘要： A method for providing a low resistance non-agglomerated Ni monosilicide contact that is useful in semiconductor devices. Where the inventive method of fabricating a substantially non-agglomerated Ni alloy monosilicide comprises the steps of: forming a metal alloy layer over a portion of a Si-containing substrate, wherein said metal alloy layer comprises of Ni and one or multiple alloying additive(s), where said alloying additive is Ti, V, Ge, Cr, Zr, Nb, Mo, Hf, Ta, W, Re, Rh, Pd or Pt or mixtures thereof; annealing the metal alloy layer at a temperature to convert a portion of said metal alloy layer into a Ni alloy monosilicide layer; and removing remaining metal alloy layer not converted into Ni alloy monosilicide. The alloying additives are selected for phase stability and to retard agglomeration. The alloying additives most efficient in retarding agglomeration are most efficient in producing silicides with low sheet resistance.

摘要翻译： 一种用于提供半导体器件中有用的低电阻非聚集Ni单硅化物接触的方法。 在制造基本上非团聚的Ni合金一硅化物的本发明方法中，包括以下步骤：在含Si衬底的一部分上形成金属合金层，其中所述金属合金层包括Ni和一种或多种合金添加剂 ），其中所述合金添加剂为Ti，V，Ge，Cr，Zr，Nb，Mo，Hf，Ta，W，Re，Rh，Pd或Pt或其混合物; 在将所述金属合金层的一部分转化为Ni合金一硅化物层的温度下退火金属合金层; 并除去未转化为Ni合金一硅化物的剩余金属合金层。 选择合金添加剂用于相稳定性并阻止团聚。 延迟聚集中最有效的合金添加剂在生产低薄层电阻的硅化物中是最有效的。