公开(公告)号：US20090008725A1

公开(公告)日：2009-01-08

申请号：US11773160

申请日：2007-07-03

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

公开(公告)号：US07189431B2

公开(公告)日：2007-03-13

申请号：US10711717

申请日：2004-09-30

申请人： Hideaki Yamasaki ,  Kazuhito Nakamura ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  Paul Jamison

发明人： Hideaki Yamasaki ,  Kazuhito Nakamura ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  Paul Jamison

IPC分类号： C23C16/16

CPC分类号： H01L21/28556 ,  C23C16/16 ,  H01L21/28079 ,  H01L21/28247 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76856 ,  H01L29/517

摘要： A method for forming a passivated metal layer that preserves the properties and morphology of an underlying metal layer during subsequent exposure to oxygen-containing ambients. The method includes providing a substrate in a process chamber, exposing the substrate to a process gas containing a rhenium-carbonyl precursor to deposit a rhenium metal layer on the substrate in a chemical vapor deposition process, and forming a passivation layer on the rhenium metal layer to thereby inhibit oxygen-induced growth of rhenium-containing nodules on the rhenium metal surface.

摘要翻译： 用于形成钝化金属层的方法，其在随后暴露于含氧环境期间保持下面的金属层的性质和形态。 该方法包括在处理室中提供衬底，将衬底暴露于含有铼 - 羰基前体的工艺气体，以在化学气相沉积工艺中在衬底上沉积铼金属层，以及在铼金属层上形成钝化层 从而抑制铼金属表面上含铼结核的氧诱导生长。

公开(公告)号：US06603181B2

公开(公告)日：2003-08-05

申请号：US09760621

申请日：2001-01-16

申请人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

发明人： Paul M. Solomon ,  Douglas A. Buchanan ,  Eduard A. Cartier ,  Kathryn W. Guarini ,  Fenton R. McFeely ,  Huiling Shang ,  John J. Yourkas

IPC分类号： H01L2976

CPC分类号： H01L29/517 ,  H01L21/263 ,  H01L21/28079 ,  H01L29/495 ,  Y10S438/91

摘要： A MOS structure processed to have a semiconductor-dielectric interface that is passivated to reduce the interface state density. An example is a MOSFET having a gate dielectric on which an electrode is present that is substantially impervious to molecular hydrogen, but sufficiently thin to be pervious to atomic hydrogen, enabling atomic hydrogen to be diffused therethrough into an underlying semiconductor-dielectric interface. Atomic hydrogen diffusion can be achieved by subjecting such an electrode to hydrogen plasma, forming the electrode of an aluminum-tungsten alloy in the presence of hydrogen, and implanting atomic hydrogen into the electrode. The latter two techniques are each followed by an anneal to cause the atomic hydrogen to diffuse through the electrode and into the semiconductor-dielectric interface.

摘要翻译： 被处理成具有钝化的半导体 - 电介质界面以降低界面态密度的MOS结构。 一个例子是具有栅电介质的MOSFET，其上存在基本上不透分子氢的电极，但是足够薄以能够透过原子氢，使原子氢能够通过其扩散到下面的半导体介电界面中。 原子氢扩散可以通过使这样的电极经受氢等离子体，在氢的存在下形成铝 - 钨合金的电极，并将原子氢注入到电极中来实现。 后两种技术之后各自进行退火以使原子氢扩散通过电极并进入半导体 - 电介质界面。

公开(公告)号：US08232647B2

公开(公告)日：2012-07-31

申请号：US12034708

申请日：2008-02-21

申请人： Chih-Chao Yang ,  Fenton R. McFeely

发明人： Chih-Chao Yang ,  Fenton R. McFeely

IPC分类号： H01L23/52

CPC分类号： H01L21/02362 ,  H01L21/743 ,  H01L21/76841 ,  H01L21/76847 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/485 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/00

摘要： A high aspect ratio metallization structure is provided in which a noble metal-containing material is present at least within a lower portion of a contact opening located in a dielectric material and is in direct contact with a metal semiconductor alloy located on an upper surface of a material stack of at least one semiconductor device. In one embodiment, the noble metal-containing material is plug located within the lower region of the contact opening and an upper region of the contact opening includes a conductive metal-containing material. The conductive metal-containing material is separated from plug of noble metal-containing material by a bottom walled portion of a U-shaped diffusion barrier. In another embodiment, the noble metal-containing material is present throughout the entire contact opening.

摘要翻译： 提供了一种高纵横比金属化结构，其中含贵金属的材料至少位于位于电介质材料中的接触开口的下部内，并且与位于电介质材料的上表面上的金属半导体合金直接接触 至少一个半导体器件的材料堆叠。 在一个实施方案中，含贵金属的材料是位于接触开口的下部区域内的插塞，并且接触开口的上部区域包括含导电金属的材料。 含有导电性金属的材料通过U形扩散阻挡层的底壁部与贵金属材料的塞分离。 在另一个实施方案中，含贵金属的材料存在于整个接触开口处。

公开(公告)号：US20110073834A1

公开(公告)日：2011-03-31

申请号：US12566870

申请日：2009-09-25

申请人： James B. Hannon ,  Fenton R. McFeely ,  Satoshi Oida ,  John J. Yurkas

发明人： James B. Hannon ,  Fenton R. McFeely ,  Satoshi Oida ,  John J. Yurkas

IPC分类号： H01L29/66 ,  H01L21/31 ,  H01L21/20

CPC分类号： H01L29/16

摘要： A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.

摘要翻译： 电活化具有形成在碳化硅层上的一个或多个石墨烯层的结构的方法包括对该结构进行氧化处理，以形成设置在碳化硅层和一个或多个石墨烯的最底部之间的氧化硅层 从而电激活最底层的石墨烯层。

公开(公告)号：US07884018B2

公开(公告)日：2011-02-08

申请号：US11850916

申请日：2007-09-06

申请人： Fenton R. McFeely ,  Chih-Chao Yang

发明人： Fenton R. McFeely ,  Chih-Chao Yang

IPC分类号： H01L21/44

CPC分类号： H01L21/76849 ,  C23C16/04 ,  C23C16/16 ,  H01L21/28562 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a noble metal cap on a conductive material embedded in a dielectric material in an interconnect structure. The method includes the step of contacting (i) a conductive material having a bare upper surface partially embedded in a dielectric material and (ii) vapor of a noble metal containing compound, in the presence of carbon monoxide and a carrier gas. The contacting step is carried out at a temperature, pressure and for a length of time sufficient to produce a noble metal cap disposed directly on the upper surface of the conductive material without substantially extending into upper surface of the dielectric material or leaving a noble metal residue onto the dielectric material.

摘要翻译： 在嵌入在互连结构中的电介质材料中的导电材料上形成贵金属盖的方法。 该方法包括以下步骤：（i）在一氧化碳和载气的存在下，具有部分嵌入电介质材料中的裸露上表面的导电材料和（ii）含贵金属的化合物的蒸气。 接触步骤在足以产生直接设置在导电材料的上表面上的贵金属帽的温度，压力和时间上进行，而基本上不延伸到电介质材料的上表面或留下贵金属残留物 到电介质材料上。

公开(公告)号：US20080245658A1

公开(公告)日：2008-10-09

申请号：US12141476

申请日：2008-06-18

申请人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

IPC分类号： C23C14/00

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US20080164579A1

公开(公告)日：2008-07-10

申请号：US11621365

申请日：2007-01-09

申请人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

发明人： Fenton R. McFeely ,  Alejandro G. Schrott ,  John J. Yurkas

IPC分类号： H01L21/20 ,  H01L29/12

CPC分类号： C23C16/30 ,  H01L21/28556 ,  H01L21/76877 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1683 ,  Y10T428/249994

摘要： A chemical vapor deposition (CVD) method for depositing materials including germanium (Ge) and antimony (Sb) which, in some embodiments, has the ability to fill high aspect ratio openings is provided. The CVD method of the instant invention permits for the control of GeSb stoichiometry over a wide range of values and the inventive method is performed at a substrate temperature of less than 400° C., which makes the inventive method compatible with existing interconnect processes and materials. In addition to the above, the inventive method is a non-selective CVD process, which means that the GeSb materials are deposited equally well on insulating and non-insulating materials.

摘要翻译： 提供了一种用于沉积包括锗（Ge）和锑（Sb）在内的材料的化学气相沉积（CVD）方法，其在一些实施例中具有填充高纵横比开口的能力。 本发明的CVD方法允许在宽范围的值范围内控制GeSb化学计量，并且本发明的方法在低于400℃的衬底温度下进行，这使得本发明的方法与现有的互连工艺和材料兼容 。 除了上述之外，本发明的方法是非选择性CVD工艺，这意味着GeSb材料在绝缘和非绝缘材料上同样良好地沉积。

公开(公告)号：US07067422B2

公开(公告)日：2006-06-27

申请号：US10830804

申请日：2004-03-31

申请人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

发明人： Kazuhito Nakamura ,  Hideaki Yamasaki ,  Yumiko Kawano ,  Gert J. Leusink ,  Fenton R. McFeely ,  John J. Yurkas ,  Vijay Narayanan

IPC分类号： H01L21/44

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517

摘要： A method for forming a tantalum-containing gate electrode structure by providing a substrate having a high-k dielectric layer thereon in a process chamber and forming a tantalum-containing layer on the high-k dielectric layer in a thermal chemical vapor deposition process by exposing the substrate to a process gas containing TAIMATA (Ta(N(CH3)2)3(NC(C2H5)(CH3)2)) precursor gas. In one embodiment of the invention, the tantalum-containing layer can include a TaSiN layer formed from a process gas containing TAIMATA precursor gas, a silicon containing gas, and optionally a nitrogen-containing gas. In another embodiment of the invention, a TaN layer is formed on the TaSiN layer. The TaN layer can be formed from a process gas containing TAIMATA precursor gas and optionally a nitrogen-containing gas. A computer readable medium executable by a processor to cause a processing system to perform the method and a processing system for forming a tantalum-containing gate electrode structure are also provided.

摘要翻译： 一种通过在处理室中提供具有高k电介质层的衬底并在热化学气相沉积工艺中在高k电介质层上形成含钽层的方法来形成含钽栅电极结构的方法， 将衬底加工成含有TAIMATA（Ta（N（CH 3）2）3）（NC（C 2）2）的工艺气体， （CH 3）2））前体气体。 在本发明的一个实施方案中，含钽层可以包括由含有TAIMATA前体气体，含硅气体和任选的含氮气体的工艺气体形成的TaSiN层。 在本发明的另一实施例中，在TaSiN层上形成TaN层。 TaN层可以由含有TAIMATA前体气体和任选的含氮气体的工艺气体形成。 还提供了可由处理器执行以使处理系统执行该方法的计算机可读介质和用于形成含钽栅电极结构的处理系统。

公开(公告)号：US06452276B1

公开(公告)日：2002-09-17

申请号：US09070394

申请日：1998-04-30

申请人： Stephan A. Cohen ,  Fenton R. McFeely ,  Cevdet I. Noyan ,  Kenneth P. Rodbell ,  John J. Yurkas ,  Robert Rosenberg

发明人： Stephan A. Cohen ,  Fenton R. McFeely ,  Cevdet I. Noyan ,  Kenneth P. Rodbell ,  John J. Yurkas ,  Robert Rosenberg

IPC分类号： H01L2348

CPC分类号： H01L21/7687 ,  H01L21/76843 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to an alpha-W layer which is employed in interconnect structures such as trench capacitors or damascene wiring levels as a diffusion barrier layer. The alpha-W layer is a single phased material that is formed by a low temperature/pressure chemical vapor deposition process using tungsten hexacarbonyl, W(CO)6, as the source material.