公开(公告)号：US5168573A

公开(公告)日：1992-12-01

申请号：US328561

申请日：1989-03-24

申请人： Tryggve Fossum ,  Dwight P. Manley ,  Francis X. McKeen ,  Michael M. Tahranian

发明人： Tryggve Fossum ,  Dwight P. Manley ,  Francis X. McKeen ,  Michael M. Tahranian

IPC分类号： G06F9/30 ,  G06F15/78 ,  G11C8/16

CPC分类号： G06F9/3013 ,  G06F15/8084 ,  G06F9/3012 ,  G11C8/16

摘要： A vector register provides the capability for simultaneously writing through at least two write ports and simultaneous reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.

摘要翻译： 向量寄存器提供通过至少两个写入端口同时写入并从至少两个读取端口同时读取的能力。 另外，提供了用于将逻辑向量寄存器中的字存储到存储体中的理发杆技术，以最小化冲突。

公开(公告)号：US5125083A

公开(公告)日：1992-06-23

申请号：US306767

申请日：1989-02-03

申请人： David B. Fite ,  Tryggve Fossum ,  Ricky C. Hetherington ,  John E. Murray ,  Jr. David A. Webb

发明人： David B. Fite ,  Tryggve Fossum ,  Ricky C. Hetherington ,  John E. Murray ,  Jr. David A. Webb

IPC分类号： G06F9/38

CPC分类号： G06F9/3816 ,  G06F9/383 ,  G06F9/3834

摘要： An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

公开(公告)号：US4994996A

公开(公告)日：1991-02-19

申请号：US306343

申请日：1989-02-03

申请人： Tryggve Fossum ,  William R. Grundmann ,  Muhammad S. Hag

发明人： Tryggve Fossum ,  William R. Grundmann ,  Muhammad S. Hag

IPC分类号： G06F7/485 ,  G06F7/50

CPC分类号： G06F7/485 ,  G06F7/49936 ,  G06F7/49947 ,  G06F7/49952

摘要： A system for subtracting two floating-point binary numbers in a pipelined floating-point adder/subtractor by aligning the two fractions for sustraction; arbitrarily designating the fraction of one of the two floating-point numbers as the subtrahend, and producing the complement of that designated fraction; adding that complement to the other fraction, normalizing the result; determining whether the result is negative and, if it is, producing the complement of the normalized result; and selecting the larger of the exponents of the two floating-point numbers, and adjusting the value of the selected exponent in accordance with the normalization of the result. The preferred system produces a sticky bit signal by aligning the two fractions for subtraction by shifting one of the two fractions to the right; determining the number of consecutive zeros in the one fraction, prior to the shifting thereof, beginning at the least significant bit position; comparing (1) the number of positions the one fraction is shifted in the aligning step, with (2) the number of consecutive zeros in the one fraction; and producing a sticky bit signal when the number of consecutive zeros is less than the number of positions the one fraction is shifted in the aligning stgep, ther sticky bit signal indicating the truncation of at least one set bit during the aligning step.

公开(公告)号：US4980817A

公开(公告)日：1990-12-25

申请号：US93499

申请日：1987-08-31

申请人： Tryggve Fossum ,  Dwight P. Manley ,  Francis X. McKeen ,  Michael M. Tehranian

发明人： Tryggve Fossum ,  Dwight P. Manley ,  Francis X. McKeen ,  Michael M. Tehranian

IPC分类号： G06F17/16 ,  G06F9/30 ,  G06F15/78 ,  G11C8/16

CPC分类号： G06F9/30141 ,  G06F15/8084 ,  G06F9/30098 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/3013 ,  G11C8/16

摘要： A vector register provides the capability for simultaneously writing through at least two write ports and simultaneously reading from at least two read ports. In addition, a barber pole technique for storing words from logical vector registers into banks is provided to minimize conflicts.

摘要翻译： 向量寄存器提供通过至少两个写入端口同时写入并同时从至少两个读取端口读取的能力。 另外，提供了用于将逻辑向量寄存器中的字存储到存储体中的理发杆技术，以最小化冲突。

公开(公告)号：US20130173893A1

公开(公告)日：2013-07-04

申请号：US13341812

申请日：2011-12-30

申请人： Nicholas Cheng Hwa Chee ,  Tryggve Fossum ,  William C. Hasenplaugh

发明人： Nicholas Cheng Hwa Chee ,  Tryggve Fossum ,  William C. Hasenplaugh

IPC分类号： G06F9/318 ,  G06F9/312

CPC分类号： G06F8/44 ,  G06F9/3001 ,  G06F9/30087 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/462 ,  G06F11/0751

摘要： Hardware compilation and/or translation with fault detection and roll back functionality are disclosed. Compilation and/or translation logic receives programs encoded in one language, and encodes the programs into a second language including instructions to support processor features not encoded into the original language encoding of the programs. In one embodiment, an execution unit executes instructions of the second language including an operation-check instruction to perform a first operation and record the first operation result for a comparison, and an operation-test instruction to perform a second operation and a fault detection operation by comparing the second operation result to the recorded first operation result. In some embodiments, an execution unit executes instructions of the second language including commit instructions to record execution checkpoint states of registers mapped to architectural registers, and roll-back instructions to restore the registers mapped to architectural registers to previously recorded execution checkpoint states.

公开(公告)号：US20120239875A1

公开(公告)日：2012-09-20

申请号：US13482713

申请日：2012-05-29

申请人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

发明人： Tryggve Fossum ,  George Chrysos ,  Todd A. Dutton

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F9/3836 ,  G06F1/3203 ,  G06F1/3287 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3869 ,  G06F9/5061 ,  G06F9/5094 ,  Y02D10/171 ,  Y02D10/22

摘要： A method and apparatus for heterogeneous chip multiprocessors (CMP) via resource restriction. In one embodiment, the method includes the accessing of a resource utilization register to identify a resource utilization policy. Once accessed, a processor controller ensures that the processor core utilizes a shared resource in a manner specified by the resource utilization policy. In one embodiment, each processor core within a CMP includes an instruction issue throttle resource utilization register, an instruction fetch throttle resource utilization register and other like ways of restricting its utilization of shared resources within a minimum and maximum utilization level. In one embodiment, resource restriction provides a flexible manner for allocating current and power resources to processor cores of a CMP that can be controlled by hardware or software. Other embodiments are described and claimed.

摘要翻译： 一种通过资源限制的异构芯片多处理器（CMP）的方法和装置。 在一个实施例中，该方法包括访问资源利用寄存器以识别资源利用策略。 一旦被访问，处理器控制器确保处理器核心以资源利用策略指定的方式利用共享资源。 在一个实施例中，CMP内的每个处理器核心包括指令发布节流阀资源利用寄存器，指令提取节流阀资源利用寄存器以及在最小和最大利用水平内限制其对共享资源的利用的类似方式。 在一个实施例中，资源限制提供了将电流和功率资源分配给可由硬件或软件控制的CMP的处理器核心的灵活方式。 描述和要求保护其他实施例。

公开(公告)号：US20100138609A1

公开(公告)日：2010-06-03

申请号：US12315331

申请日：2008-12-02

申请人： William Hasenplaugh ,  Joel Emer ,  Tryggve Fossum ,  Aamer Jaleel ,  Simon Steely

发明人： William Hasenplaugh ,  Joel Emer ,  Tryggve Fossum ,  Aamer Jaleel ,  Simon Steely

IPC分类号： G06F12/00 ,  G06F9/46

CPC分类号： G06F12/0802 ,  G06F9/5016 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2209/501 ,  Y02D10/22

摘要： A technique to enable resource allocation optimization within a computer system. In one embodiment, a gradient partition algorithm (GPA) module is used to continually measure performance and adjust allocation to shared resources among a plurality of data classes in order to achieve optimal performance.

摘要翻译： 一种在计算机系统内实现资源分配优化的技术。 在一个实施例中，使用梯度分割算法（GPA）模块来连续地测量性能并且调整对多个数据类之间的共享资源的分配，以便实现最佳性能。

公开(公告)号：US20060156153A1

公开(公告)日：2006-07-13

申请号：US11012979

申请日：2004-12-14

申请人： Tryggve Fossum ,  Yaron Shragai ,  Shubhendu Mukherjee

发明人： Tryggve Fossum ,  Yaron Shragai ,  Shubhendu Mukherjee

IPC分类号： H04L1/00 ,  H03M13/00 ,  G08C25/00 ,  G06F11/00 ,  G06F11/30

CPC分类号： G06F11/0721 ,  G06F11/0793

摘要： An error handling routine of a processor, executing in response to a first detected unrecoverable error (DUE) of the processor, responding to an indication that a second DUE has occurred by evaluating the effect of the second DUE on the correctness of the error handling routine.

摘要翻译： 处理器的错误处理程序，响应于处理器的第一检测到的不可恢复错误（DUE）执行，响应于通过评估第二DUE对错误处理例程的正确性的影响而发生第二DUE的指示 。

公开(公告)号：US5142631A

公开(公告)日：1992-08-25

申请号：US306773

申请日：1989-02-03

申请人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

发明人： John E. Murray ,  Mark A. Firstenberg ,  David B. Fite ,  Michael M. McKeon ,  Wiliam R. Grundmann ,  David A. Webb, Jr. ,  Ronald M. Salett ,  Tryggve Fossum ,  Dwight P. Manley ,  Ricky C. Hetherington

IPC分类号： G06F9/38

CPC分类号： G06F9/355 ,  G06F9/345 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3857

摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

公开(公告)号：US5093775A

公开(公告)日：1992-03-03

申请号：US549611

申请日：1983-11-07

申请人： William R. Grundmann ,  Raymond F. Boucher ,  Tryggve Fossum

发明人： William R. Grundmann ,  Raymond F. Boucher ,  Tryggve Fossum

IPC分类号： G06F9/22 ,  G06F9/28

CPC分类号： G06F9/28

摘要： A microcode control system for a digital data processor. The processor sequentially processes data in response to a microinstruction in a data processing path including a plurality of successive processing stages. A control path parallels the data processing path and includes a plurality of stage which transfer the microinstruction in synchronism with the transfer of data through the data processing path. At each stage in the control path, the microinstruction is decoded to determine the operation to be performed in response thereto on the data by the stage in the data processing path, and control signals are generated to control the processing by the stage in the data processing path.

摘要翻译： 一种用于数字数据处理器的微代码控制系统。 处理器响应于包括多个连续处理级的数据处理路径中的微指令顺序地处理数据。 控制路径平行于数据处理路径并且包括多个级，其通过数据处理路径与数据的传送同步地传送微指令。 在控制路径中的每个阶段，对微指令进行解码，以确定响应于该数据处理路径中的阶段对数据执行的操作，并且生成控制信号以控制数据处理中的阶段的处理 路径。