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    Decision feedback equalizer and clock and data recovery circuit for high speed applications
    21.
    发明授权
    Decision feedback equalizer and clock and data recovery circuit for high speed applications 有权
    决策反馈均衡器和时钟和数据恢复电路，适用于高速应用

    公开(公告)号：US07436882B2

    公开(公告)日：2008-10-14

    申请号：US10774965

    申请日：2004-02-09

    Applicant: Afshin Momtaz

    Inventor： Afshin Momtaz

    IPC: H03H7/30 ,  H03K5/159 ,  H03D3/24

    CPC classification number: H04L25/03057 ,  H04B10/2507 ,  H04L7/0004 ,  H04L7/033 ,  H04L2025/0349

    Abstract: A method for communicating data includes equalizing received data to reduce channel related distortion in the received data. A clock having frequency and/or phase fixed relative to the equalized data is extracted from the equalized data. The extracted clock is used to clock a retimer to generate recovered data.

    Abstract translation: 用于传送数据的方法包括均衡接收的数据以减少接收到的数据中的信道相关失真。 从均衡数据中提取相对于均衡数据具有频率和/或相位固定的时钟。 提取的时钟用于对重定时器进行计时以产生恢复的数据。

    Apparatus and method for analog-to-digital converter calibration
    23.
    发明申请
    Apparatus and method for analog-to-digital converter calibration 有权
    用于模数转换器校准的装置和方法

    公开(公告)号：US20080150772A1

    公开(公告)日：2008-06-26

    申请号：US12000757

    申请日：2007-12-17

    Applicant: Jun Cao ,  Afshin Momtaz

    Inventor： Jun Cao ,  Afshin Momtaz

    IPC: H03M1/10

    CPC classification number: H03M1/1061 ,  H03M1/362

    Abstract: Methods, systems, and apparatuses for calibration of analog to digital converters (ADC) are described herein. In an aspect, an ADC includes a plurality of slices. Each slice includes a digital to analog converter (DAC), a comparator, and a digital processing unit (DPU). The digital processing unit is electrically connected to the comparator and the DAC. In another aspect, an analog-to-digital converter includes an input module and an analog to digital converter core configured to receive an analog input from the input module and generate a digital output. The ADC is configured to adjust a precision of the analog to digital converter core based on a quality of the analog input signal.

    Abstract translation: 本文描述了用于模数转换器（ADC）的校准的方法，系统和装置。 在一方面，ADC包括多个切片。 每个片包括数模转换器（DAC），比较器和数字处理单元（DPU）。 数字处理单元电连接到比较器和DAC。 在另一方面，模数转换器包括被配置为从输入模块接收模拟输入并产生数字输出的输入模块和模数转换器内核。 ADC配置为基于模拟输入信号的质量来调整模数转换器内核的精度。

    Automatic gain control with three states of operation
    24.
    发明授权
    Automatic gain control with three states of operation 失效
    具有三种运行状态的自动增益控制

    公开(公告)号：US07385449B2

    公开(公告)日：2008-06-10

    申请号：US11729587

    申请日：2007-03-29

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03G3/10

    CPC classification number: H03F3/45973 ,  H03F2200/435 ,  H03F2200/78 ,  H03G3/001 ,  H03G3/30

    Abstract: A method and apparatus for an automatic gain control circuit (AGC) that utilizes freezing and unfreezing states. A freezing process moves the AGC into a TRANSITION state from a NORMAL state, based on net change of VGA gain control codes over a monitoring time window. The freezing process then moves the AGC into a FROZEN state from the TRANSITION state, based on net change of VGA gain control codes over the monitoring time window. An unfreezing process moves the AGC into the NORMAL state from the FROZEN state, based on signal amplitude changes at the output of the VGA or other parameters of the VGA.

    Abstract translation: 一种利用冷冻和解​​冻状态的自动增益控制电路（AGC）的方法和装置。 基于监视时间窗口的VGA增益控制代码的净变化，冻结过程将AGC从NORMAL状态移动到TRANSITION状态。 基于监视时间窗口的VGA增益控制代码的净变化，冷冻过程然后将AGC从TRANSITION状态移动到FROZEN状态。 基于VGA输出端的VGA信号幅度变化或VGA的其他参数，解冻过程会将AGC从FROZEN状态移动到NORMAL状态。

    Digitally controlled threshold adjustment circuit
    26.
    发明授权
    Digitally controlled threshold adjustment circuit 有权
    数字控制阈值调节电路

    公开(公告)号：US07215171B2

    公开(公告)日：2007-05-08

    申请号：US11117767

    申请日：2005-04-28

    Applicant: Namik Kemal Kocaman ,  Afshin Momtaz

    Inventor： Namik Kemal Kocaman ,  Afshin Momtaz

    IPC: H03L5/00

    CPC classification number: H03K5/151 ,  H03K5/003 ,  H03K5/086

    Abstract: A threshold adjustment circuit including: a current DAC for supplying or sinking a varying current; a differential pair of thin oxide transistors coupled to the DAC and coupled together at a common source node; a power supply for providing a supply voltage having a voltage level above reliability of the thin oxide transistors; and a third transistor for maintaining voltage of the common source node above a predetermined level and to disable the threshold adjustment circuit. The bulk and source of each of the differential pair thin oxide transistors is coupled to the common source node and each of the differential pair thin oxide transistors is switched by a signal to keep each of the differential pair thin oxide transistors in saturation region.

    Abstract translation: 一种阈值调整电路，包括：用于提供或吸收变化电流的电流DAC; 耦合到DAC并在公共源节点处耦合在一起的薄氧化物晶体管的差分对; 用于提供具有高于薄氧化物晶体管的可靠性的电压电平的电源电压的电源; 以及第三晶体管，用于将公共源节点的电压维持在预定电平以上并禁止阈值调整电路。 每个差分对薄氧化物晶体管的体积和源极耦合到公共源节点，并且每个差分对薄氧化物晶体管被信号切换，以将每个差分对薄氧化物晶体管保持在饱和区域。

    State based algorithm to minimize mean squared error
    27.
    发明申请
    State based algorithm to minimize mean squared error 失效
    基于状态的算法来最小化均方误差

    公开(公告)号：US20060251195A1

    公开(公告)日：2006-11-09

    申请号：US11124598

    申请日：2005-05-05

    Applicant: Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Afshin Momtaz ,  Hong Chen

    Inventor： Chung-Jue Chen ,  Vasudevan Parthasarathy ,  Afshin Momtaz ,  Hong Chen

    IPC: H04B1/10

    CPC classification number: H04L25/03057 ,  H04L2025/03687

    Abstract: Data error such as mean square error may be reduced in a system such as a communication receiver using a dithering algorithm that adjusts one or more parameters in the system. The dithering algorithm may be applied to more than one parameter. The dithering algorithm may include a state machine to alter the rate of change dependent on the state of the dithering algorithm.

    Abstract translation: 在诸如使用调整系统中的一个或多个参数的抖动算法的通信接收机的系统中，诸如均方误差之类的数据误差可能会降低。 抖动算法可以应用于多个参数。 抖动算法可以包括状态机来改变取决于抖动算法的状态的变化率。

    Integrated decision feedback equalizer and clock and data recovery
    28.
    发明申请
    Integrated decision feedback equalizer and clock and data recovery 失效
    集成决策反馈均衡器和时钟和数据恢复

    公开(公告)号：US20050135471A1

    公开(公告)日：2005-06-23

    申请号：US10823252

    申请日：2004-04-13

    Applicant: Davide Tonietto ,  Afshin Momtaz

    Inventor： Davide Tonietto ,  Afshin Momtaz

    IPC: H03L7/08 ,  H03L7/089 ,  H03L7/091 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H03K5/159

    CPC classification number: H04L25/03057 ,  H03L7/0807 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0087 ,  H04L7/033 ,  H04L2025/0349

    Abstract: In an integrated decision feedback equalizer and clock and data recovery circuit one or more flip-flops and/or latches may be shared. One or more flip-flops and/or latches may be used in retiming operations in a decision feedback equalizer and in phase detection operations in a clock recovery circuit. Outputs of the flip-flops and/or latches may be used to generate feedback signals for the decision feedback equalizer. The output of a flip-flop and/or latches may be used to generate signals that drive a charge pump in the clock recovery circuit.

    Abstract translation: 在集成判决反馈均衡器和时钟和数据恢复电路中，可以共享一个或多个触发器和/或锁存器。 一个或多个触发器和/或锁存器可用于判决反馈均衡器中的重新定时操作以及时钟恢复电路中的相位检测操作。 可以使用触发器和/或锁存器的输出来产生用于判决反馈均衡器的反馈信号。 触发器和/或锁存器的输出可用于产生驱动时钟恢复电路中的电荷泵的信号。

    Phase-locked loop circuit
    29.
    发明授权
    Phase-locked loop circuit 有权
    锁相环电路

    公开(公告)号：US06909762B2

    公开(公告)日：2005-06-21

    申请号：US10843181

    申请日：2004-05-11

    Applicant: Jun Cao ,  Afshin Momtaz

    Inventor： Jun Cao ,  Afshin Momtaz

    IPC: H03L7/00 ,  H03L7/095 ,  H03L7/10 ,  H03D3/24

    CPC classification number: H03L7/10 ,  H03L7/095 ,  Y10S331/02

    Abstract: Method and circuitry for improving the accuracy and efficiency of a phase-locked loop. More specifically, the present invention relates to a method and device for monitoring the frequency discrepancy between two signals in conjunction with at least one data signal so as to improve the accuracy and efficiency of a phase-locked loop. In one embodiment of the present invention, two counters are used to check the frequency differential between a VCO signal and an external reference or input signal. An adjustable threshold is provided to determine whether the frequencies of the two signals are considered to be in a frequency-locked mode. A pair of flip-flops is used to minimize any erroneous detection of frequency discrepancy by validating two consecutive results of the frequency differential check. In addition, a data present signal is used to control the transition between the phase-locked mode and the frequency-locked mode to minimize the potential data loss.

    Abstract translation: 用于提高锁相环的精度和效率的方法和电路。 更具体地，本发明涉及一种用于监视两个信号之间的频率差异与至少一个数据信号的方法和装置，以便提高锁相环的精度和效率。 在本发明的一个实施例中，使用两个计数器来检查VCO信号和外部基准或输入信号之间的频率差。 提供可调阈值以确定两个信号的频率是否被认为处于频率锁定模式。 一对触发器用于通过验证频率差分检查的两个连续结果来最小化频率差异的任何错误检测。 另外，使用数据存在信号来控制锁相模式和锁频模式之间的转换，以最小化潜在的数据丢失。

    High speed peak amplitude comparator
    30.
    发明申请
    High speed peak amplitude comparator 有权

    公开(公告)号：US20050122137A1

    公开(公告)日：2005-06-09

    申请号：US11031102

    申请日：2005-01-06

    Applicant: Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

    Inventor： Afshin Momtaz ,  Wee-Guan Tan ,  Armond Hairapetian

    IPC: G01R19/04 ,  H03K5/1532 ,  H03K5/153

    CPC classification number: H03K5/1532 ,  G01R19/04

    Abstract: Various methods and circuits for implementing high speed peak amplitude comparison. The invention achieves higher speed of operation by eliminating the slow feedback loop commonly employed in peak detection. In one embodiment, the invention directly compares a signal that represents the peak amplitude of the input signal minus a small voltage drop, to a modified reference voltage. The modified reference voltage corresponds to the reference voltage that is adjusted to compensate for the small voltage drop in the maximum input voltage. In another embodiment, the invention implements a differential version of the peak amplitude comparator to obtain better noise rejection and reduced effective offset among other advantages.

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