公开(公告)号：US20120001614A1

公开(公告)日：2012-01-05

申请号：US13232395

申请日：2011-09-14

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01R1/30 ,  G01N27/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US08052931B2

公开(公告)日：2011-11-08

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： G01N15/06 ,  G01N33/00

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20110163812A1

公开(公告)日：2011-07-07

申请号：US12651504

申请日：2010-01-04

申请人： Aditya Bansal ,  Sufi Zafar

发明人： Aditya Bansal ,  Sufi Zafar

IPC分类号： H03F3/16

CPC分类号： H03F3/70 ,  G01N27/4145 ,  Y10T436/11

摘要： An apparatus configured to identify a material having an electric charge, the apparatus having: an inverting gain amplifier including a first field-effect transistor (FET) coupled to a second FET; wherein a gate of the first FET is configured to sense the electric charge and an output of the amplifier provides a measurement of the electric charge to identify the material.

摘要翻译： 一种被配置为识别具有电荷的材料的装置，所述装置具有：反相增益放大器，包括耦合到第二FET的第一场效应晶体管（FET）; 其中第一FET的栅极被配置为感测电荷，并且放大器的输出提供电荷的测量以识别材料。

公开(公告)号：US20080191292A1

公开(公告)日：2008-08-14

申请号：US11673901

申请日：2007-02-12

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/49 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US20080017936A1

公开(公告)日：2008-01-24

申请号：US11477707

申请日：2006-06-29

申请人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/78

摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.

摘要翻译： 提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。 公开了nFET和/或pFET结构。 根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在 电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

公开(公告)号：US20110033952A1

公开(公告)日：2011-02-10

申请号：US12537063

申请日：2009-08-06

申请人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

发明人： Marwan H. Khater ,  Tak H. Ning ,  Lidija Sekaric ,  Sufi Zafar

IPC分类号： G01N33/543 ,  H01L29/78

CPC分类号： G01N33/54373 ,  B82Y10/00 ,  G01N27/3276 ,  G01N27/4145 ,  G01N33/543 ,  H01L29/785 ,  Y10S977/721 ,  Y10S977/92 ,  Y10S977/953

摘要： A sensor for biomolecules includes a silicon fin comprising undoped silicon; a source region adjacent to the silicon fin, the source region comprising heavily doped silicon; a drain region adjacent to the silicon fin, the drain region comprising heavily doped silicon of a doping type that is the same doping type as that of the source region; and a layer of a gate dielectric covering an exterior portion of the silicon fin between the source region and the drain region, the gate dielectric comprising a plurality of antibodies, the plurality of antibodies configured to bind with the biomolecules, such that a drain current flowing between the source region and the drain region varies when the biomolecules bind with the antibodies.

摘要翻译： 用于生物分子的传感器包括包含未掺杂硅的硅片; 与硅鳍片相邻的源极区域，源极区域包括重掺杂的硅; 与所述硅鳍片相邻的漏极区域，所述漏极区域包括掺杂类型的与所述源极区域相同的掺杂类型的重掺杂硅; 以及覆盖源极区域和漏极区域之间的硅鳍片的外部部分的栅极电介质层，所述栅极电介质包括多个抗体，所述多个抗体被配置为与所述生物分子结合，使得漏极电流流动 当生物分子与抗体结合时，在源区和漏区之间变化。

公开(公告)号：US20100044805A1

公开(公告)日：2010-02-25

申请号：US12609555

申请日：2009-10-30

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Barry P. Linder ,  Renee T. Mo ,  Vijay Narayanan ,  Dae-Gyu Park ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/78

CPC分类号： H01L21/28088 ,  H01L21/28518 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： A multilayered gate stack having improved reliability (i.e., low charge trapping and gate leakage degradation) is provided. The inventive multilayered gate stack includes, from bottom to top, a metal nitrogen-containing layer located on a surface of a high-k gate dielectric and Si-containing conductor located directly on a surface of the metal nitrogen-containing layer. The improved reliability is achieved by utilizing a metal nitrogen-containing layer having a compositional ratio of metal to nitrogen of less than 1.1. The inventive gate stack can be useful as an element of a complementary metal oxide semiconductor (CMOS). The present invention also provides a method of fabricating such a gate stack in which the process conditions of a sputtering process are varied to control the ratio of metal and nitrogen within the sputter deposited layer.

摘要翻译： 提供了具有改进的可靠性（即，低电荷捕获和栅极泄漏劣化）的多层栅极堆叠。 本发明的多层栅极堆叠包括位于位于金属含氮层的表面上的高k栅极电介质和含Si导体的表面上的含金属层的底部至顶部。 通过利用具有小于1.1的金属与氮的组成比的金属含氮层来实现提高的可靠性。 本发明的栅叠层可用作互补金属氧化物半导体（CMOS）的元件。 本发明还提供一种制造这种栅叠层的方法，其中改变溅射工艺的工艺条件以控制溅射沉积层内的金属和氮的比例。

公开(公告)号：US07521346B2

公开(公告)日：2009-04-21

申请号：US11875524

申请日：2007-10-19

申请人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

IPC分类号： H01L21/4763

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US06982230B2

公开(公告)日：2006-01-03

申请号：US10291334

申请日：2002-11-08

申请人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

发明人： Cyril Cabral, Jr. ,  Alessandro C. Callegari ,  Michael A. Gribelyuk ,  Paul C. Jamison ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Vijay Narayanan ,  Deborah A. Neumayer ,  Pushkar Ranade ,  Sufi Zafar

IPC分类号： H01L21/31

CPC分类号： H01L21/02181 ,  C23C16/405 ,  C23C16/56 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/02271 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/31604 ,  H01L21/823857 ,  H01L27/0805 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating hafnium oxide and/or zirconium oxide films is provided. The methods include providing a mixture of Hf and/or Zr alkoxide dissolved, emulsified or suspended in a liquid; vaporizing at least the alkoxide and depositing the vaporized component at a temperature of greater than 400° C. The resultant film is dense, microcrystalline and is capable of self-passivation when treated in a hydrogen plasma or forming gas anneal.

公开(公告)号：US09417208B2

公开(公告)日：2016-08-16

申请号：US13571389

申请日：2012-08-10

申请人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

发明人： Donald Dorman ,  Tak Ning ,  Sufi Zafar

IPC分类号： G01N27/414 ,  G01N27/333 ,  G01N27/327

CPC分类号： G01N27/4145 ,  G01N27/3271 ,  G01N27/3335 ,  G01N27/414

摘要： A method for operating a sensor for biomolecules or charged ions, the sensor comprising a first field effect transistor (FET) and a second FET, wherein the first FET and the second FET comprise a shared node includes placing an electrolyte containing the biomolecules or charged ions on a sensing surface of the sensor, the electrolyte comprising a gate of the second FET; applying an inversion voltage to a gate of the first FET; making a first electrical connection to an unshared node of the first FET; making a second electrical connection to unshared node of the second FET; determining a change in a drain current flowing between the unshared node of the first FET and the unshared node of the second FET; and determining an amount of biomolecules or charged ions contained in the electrolyte based on the determined change in the drain current.

摘要翻译： 一种用于操作用于生物分子或带电离子的传感器的方法，所述传感器包括第一场效应晶体管（FET）和第二FET，其中所述第一FET和所述第二FET包括共享节点，包括放置含有所述生物分子或带电离子的电解质 在所述传感器的感测表面上，所述电解质包括所述第二FET的栅极; 对第一FET的栅极施加反转电压; 与第一FET的非共享节点进行第一电连接; 与第二FET的非共享节点进行第二电连接; 确定在所述第一FET的非共享节点和所述第二FET的非共享节点之间流动的漏极电流的变化; 以及基于确定的漏极电流的变化来确定电解质中包含的生物分子或带电离子的量。