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公开(公告)号：US20120187566A1
公开(公告)日：2012-07-26
申请号：US13013108
申请日：2011-01-25
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： H01L23/522 , H01L21/76802 , H01L21/7682 , H01L21/76885 , H01L21/76897 , H01L23/5222 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.
摘要翻译： 公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。 该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件 离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。
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22.发明申请公开(公告)号：US20120086128A1
公开(公告)日：2012-04-12
申请号：US12899911
申请日：2010-10-07
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L23/528 , H01L21/76885 , H01L21/76897 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A metal layer is deposited on a planar surface on which top surfaces of underlying metal vias are exposed. The metal layer is patterned to form at least one metal block, which has a horizontal cross-sectional area of a metal line to be formed and at least one overlying metal via to be formed. Each upper portion of underlying metal vias is recessed outside of the area of a metal block located directly above. The upper portion of the at least one metal block is lithographically patterned to form an integrated line and via structure including a metal line having a substantially constant width and at least one overlying metal via having the same substantially constant width and borderlessly aligned to the metal line. An overlying-level dielectric material layer is deposited and planarized so that top surface(s) of the at least one overlying metal via is/are exposed.
摘要翻译： 金属层沉积在其上暴露下面的金属通孔的顶表面的平坦表面上。 图案化金属层以形成至少一个金属块，其具有要形成的金属线的水平横截面积和要形成的至少一个上覆的金属通孔。 下面的金属通孔的每个上部凹陷在位于正上方的金属块的区域的外部。 至少一个金属块的上部被光刻地图案化以形成集成线和通孔结构，其包括具有基本上恒定的宽度的金属线和至少一个覆盖的金属通孔，其具有相同的基本上恒定的宽度并且与金属线无边界地对准 。 沉积和平坦化上层电介质材料层，使得至少一个上覆金属通孔的顶表面被暴露。
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公开(公告)号：US08835305B2
公开(公告)日：2014-09-16
申请号：US13562953
申请日：2012-07-31
申请人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
发明人： Chih-Chao Yang , Shyng-Tsong Chen , Samuel S. Choi , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Wai-Kin Li , Christopher J. Penny , Shom Ponoth , Yunpeng Yin
IPC分类号： H01L21/4763 , H01L23/12 , H01L21/768 , H01L23/522
CPC分类号： H01L23/53295 , H01L21/76807 , H01L21/76813 , H01L21/76831 , H01L21/76844 , H01L23/481 , H01L23/5226 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： The profile of a via can be controlled by forming a profile control liner within each via opening that is formed into a dielectric material prior to forming a line opening within the dielectric material. The presence of the profile control liner within each via opening during the formation of the line opening prevents rounding of the corners of a dielectric material portion that is present beneath the line opening and adjacent the via opening.
摘要翻译： 可以通过在形成介电材料之前形成电介质材料的每个通孔开口内形成轮廓控制衬垫来控制通孔的轮廓，然后在电介质材料内形成线路开口。 在形成线路开口期间在每个通孔开口内存在轮廓控制衬垫防止存在于线路开口下方并且邻近通孔开口的电介质材料部分的拐角的四舍五入。
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24.发明授权Method of forming a borderless contact structure employing dual etch stop layers 失效使用双蚀刻停止层形成无边界接触结构的方法公开(公告)号：US08765585B2
公开(公告)日：2014-07-01
申请号：US13095955
申请日：2011-04-28
IPC分类号： H01L21/311 , H01L21/336
CPC分类号： H01L29/78 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41775 , H01L29/66545
摘要： Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.
摘要翻译： 形成在衬底上的每个栅极结构包括栅极电介质，栅极导体，第一蚀刻停止层和栅极盖电介质。 在栅极结构，栅极间隔物以及源极和漏极区域上形成第二蚀刻停止层。 在第二蚀刻停止层上方形成第一接触电介质层和第二接触电介质层。 形成至少延伸到栅极盖电介质的顶表面的栅极接触通孔。 随后形成延伸到第一和第二接触电介质层之间的界面的源极/漏极接触孔。 通过同时蚀刻暴露的栅极帽电介质和第一接触电介质层的暴露部分，然后同时蚀刻第一和第二蚀刻停止层，使各种接触通孔垂直延伸。 从而形成与外表面自对准的源极/漏极接触孔。
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25.发明申请MASK FREE PROTECTION OF WORK FUNCTION MATERIAL PORTIONS IN WIDE REPLACEMENT GATE ELECTRODES 有权工作功能的绝对保护功能材料部分在更换门电极公开(公告)号：US20130307086A1
公开(公告)日：2013-11-21
申请号：US13471852
申请日：2012-05-15
IPC分类号： H01L27/088 , H01L21/283
CPC分类号： H01L29/401 , E21B43/305 , E21B47/122 , H01L21/823431 , H01L21/823456 , H01L21/845 , H01L27/088 , H01L27/0886 , H01L27/1211
摘要： In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.
摘要翻译： 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。
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公开(公告)号：US08525339B2
公开(公告)日：2013-09-03
申请号：US13191999
申请日：2011-07-27
CPC分类号： H01L23/53238 , H01L21/76841 , H01L21/76843 , H01L21/76847 , H01L21/76877 , H01L21/76882 , H01L2924/0002 , H01L2924/00
摘要： A hybrid interconnect structure containing copper regions that have different impurities levels within a same opening is provided. In one embodiment, the interconnect structure includes a patterned dielectric material having at least one opening located therein. A dual material liner is located at least on sidewalls of the patterned dielectric material within the at least one opening. The structure further includes a first copper region having a first impurity level located within a bottom region of the at least one opening and a second copper region having a second impurity level located within a top region of the at least one opening and atop the first copper region. In accordance with the present disclosure, the first impurity level of the first copper region is different from the second impurity level of the second copper region.
摘要翻译： 提供了包含在相同开口内具有不同杂质水平的铜区域的混合互连结构。 在一个实施例中，互连结构包括具有位于其中的至少一个开口的图案化电介质材料。 双材料衬垫至少位于所述至少一个开口内的图案化电介质材料的侧壁上。 所述结构还包括具有位于所述至少一个开口的底部区域内的第一杂质水平的第一铜区域和具有位于所述至少一个开口的顶部区域内的第二杂质水平的第二铜区域和位于所述第一铜 地区。 根据本公开，第一铜区域的第一杂质水平不同于第二铜区域的第二杂质水平。
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公开(公告)号：US20130043556A1
公开(公告)日：2013-02-21
申请号：US13211351
申请日：2011-08-17
IPC分类号： H01L23/525 , H01L21/28 , H01L21/20 , H01L23/48
CPC分类号： H01L21/76877 , H01L23/5256 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A size-filtered metal interconnect structure allows formation of metal structures having different compositions. Trenches having different widths are formed in a dielectric material layer. A blocking material layer is conformally deposited to completely fill trenches having a width less than a threshold width. An isotropic etch is performed to remove the blocking material layer in wide trenches, i.e., trenches having a width greater than the threshold width, while narrow trenches, i.e., trenches having a width less than the threshold width, remain plugged with remaining portions of the blocking material layer. The wide trenches are filled and planarized with a first metal to form first metal structures having a width greater than the critical width. The remaining portions of the blocking material layer are removed to form cavities, which are filled with a second metal to form second metal structures having a width less than the critical width.
摘要翻译： 尺寸过滤的金属互连结构允许形成具有不同组成的金属结构。 在介电材料层中形成具有不同宽度的沟槽。 保形材料层被共形沉积以完全填充具有小于阈值宽度的宽度的沟槽。 执行各向同性蚀刻以去除宽沟槽中的阻挡材料层，即具有大于阈值宽度的宽度的沟槽，而窄沟槽（即，具有小于阈值宽度的宽度的沟槽）保持与所述阈值宽度的剩余部分 阻挡材料层。 宽沟槽用第一金属填充和平坦化，以形成具有大于临界宽度的宽度的第一金属结构。 去除阻挡材料层的剩余部分以形成空腔，其中填充有第二金属以形成具有小于临界宽度的宽度的第二金属结构。
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公开(公告)号：US20120273848A1
公开(公告)日：2012-11-01
申请号：US13095955
申请日：2011-04-28
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/78 , H01L21/76816 , H01L21/76834 , H01L21/76897 , H01L21/823418 , H01L21/823437 , H01L21/84 , H01L27/1203 , H01L29/41775 , H01L29/66545
摘要： Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.
摘要翻译： 形成在衬底上的每个栅极结构包括栅极电介质，栅极导体，第一蚀刻停止层和栅极盖电介质。 在栅极结构，栅极间隔物以及源极和漏极区域上形成第二蚀刻停止层。 在第二蚀刻停止层上形成第一接触电介质层和第二接触电介质层。 形成至少延伸到栅极盖电介质的顶表面的栅极接触通孔。 随后形成延伸到第一和第二接触电介质层之间的界面的源极/漏极接触孔。 通过同时蚀刻暴露的栅极帽电介质和第一接触电介质层的暴露部分，然后同时蚀刻第一和第二蚀刻停止层，使各种接触通孔垂直延伸。 从而形成与外表面自对准的源极/漏极接触孔。
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公开(公告)号：US09620619B2
公开(公告)日：2017-04-11
申请号：US13348894
申请日：2012-01-12
申请人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
发明人： Veeraraghavan S. Basker , David V. Horak , Charles W. Koburger, III , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/20 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/76897 , H01L29/66628 , H01L29/78
摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.
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公开(公告)号：US09059254B2
公开(公告)日：2015-06-16
申请号：US13604660
申请日：2012-09-06
IPC分类号： H01L21/44 , H01L21/768 , H01L21/311
CPC分类号： H01L23/528 , H01L21/31144 , H01L21/76807 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。
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