公开(公告)号：US06218300B1

公开(公告)日：2001-04-17

申请号：US09097301

申请日：1998-06-12

Applicant: Pravin K. Narwankar ,  Turgut Sahin ,  Randall S. Urdahl ,  Ankineedu Velaga ,  Patricia Liu

Inventor： Pravin K. Narwankar ,  Turgut Sahin ,  Randall S. Urdahl ,  Ankineedu Velaga ,  Patricia Liu

IPC: H01L2144

CPC classification number: C23C16/405

Abstract: A method and apparatus for forming a titanium doped tantalum pentaoxide dielectric using a CVD process. According to the present invention a substrate is placed in the deposition chamber. A source of tantalum, a source of titanium, and an oxygen containing gas are then fed into the chamber. Thermal energy is used to decompose the source of tantalum to form tantalum atoms, and decompose the source of titanium to form titanium atoms in the deposition chamber. The titanium atoms, tantalum atoms and the oxygen containing gas then react to form a tantalum pentaoxide dielectric film doped with titanium.

Abstract translation: 使用CVD工艺形成掺杂钛的五氧化钽电介质的方法和装置。 根据本发明，将基板放置在沉积室中。 然后将钽源，钛源和含氧气体进料到室中。 热能用于分解钽源以形成钽原子，并且在沉积室中分解钛源以形成钛原子。 然后，钛原子，钽原子和含氧气体反应形成掺杂有钛的五氧化钽电介质膜。

公开(公告)号：US20200024736A1

公开(公告)日：2020-01-23

申请号：US16515875

申请日：2019-07-18

Applicant: Kaushal Gangakhedkar ,  Jonathan Frankel ,  Colin C. Neikirk ,  Pravin K. Narwankar

Inventor： Kaushal Gangakhedkar ,  Jonathan Frankel ,  Colin C. Neikirk ,  Pravin K. Narwankar

IPC: C23C16/455 ,  C23C16/44 ,  A61K9/16

Abstract: A reactor for coating particles includes a vacuum chamber configured to hold particles to be coated, a vacuum port to exhaust gas from the vacuum chamber via the outlet of the vacuum chamber, a chemical delivery system configured to flow a process gas into the particles via a gas inlet on the vacuum chamber, one or more vibrational actuators located on a first mounting surface of the vacuum chamber, and a controller configured to cause the one or more vibrational actuators to generate a vibrational motion in the vacuum chamber sufficient to induce a vibrational motion in the particles held within the vacuum chamber.

公开(公告)号：US09748125B2

公开(公告)日：2017-08-29

申请号：US13755891

申请日：2013-01-31

Applicant: Banqiu Wu ,  Nag B. Patibandla ,  Toshiaki Fujita ,  Ralf Hofmann ,  Pravin K. Narwankar ,  Jeonghoon Oh ,  Srinivas Satya ,  Li-Qun Xia

Inventor： Banqiu Wu ,  Nag B. Patibandla ,  Toshiaki Fujita ,  Ralf Hofmann ,  Pravin K. Narwankar ,  Jeonghoon Oh ,  Srinivas Satya ,  Li-Qun Xia

IPC: C23C16/00 ,  H01L21/00 ,  H01L21/673 ,  H01L21/677 ,  C23C16/455 ,  C23C16/458 ,  C23C16/54

CPC classification number: H01L21/673 ,  C23C16/45546 ,  C23C16/4558 ,  C23C16/4584 ,  C23C16/54 ,  H01L21/67346 ,  H01L21/677

Abstract: A processing chamber having a plurality of movable substrate carriers stacked therein for continuously processing a plurality of substrates is provided. The movable substrate carrier is capable of being transported from outside of the processing chamber, e.g., being transferred from a load luck chamber, into the processing chamber and out of the processing chamber, e.g., being transferred into another load luck chamber. Process gases delivered into the processing chamber are spatially separated into a plurality of processing slots, and/or temporally controlled. The processing chamber can be part of a multi-chamber substrate processing system.

公开(公告)号：US09305838B2

公开(公告)日：2016-04-05

申请号：US13601963

申请日：2012-08-31

Applicant: Pravin K. Narwankar ,  Joe Griffith Cruz ,  Arvind Sundarrajan ,  Murali Narasimhan ,  Subbalakshmi Sreekala ,  Victor Pushparaj

Inventor： Pravin K. Narwankar ,  Joe Griffith Cruz ,  Arvind Sundarrajan ,  Murali Narasimhan ,  Subbalakshmi Sreekala ,  Victor Pushparaj

IPC: H01L29/41 ,  H01L21/768 ,  A61Q9/04 ,  H01L23/538 ,  A61K8/46 ,  A61K8/81 ,  B82Y40/00

CPC classification number: H01L21/76877 ,  A61K8/46 ,  A61K8/8182 ,  A61K2800/884 ,  A61Q9/04 ,  B82Y40/00 ,  H01L21/76843 ,  H01L23/5384 ,  H01L29/413 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

Abstract: An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.

Abstract translation: 具有BEOL互连的集成电路可以包括：包括半导体器件的衬底; 在所述衬底的表面上的第一层电介质，所述第一层电介质包括用于与所述半导体器件电接触的填充通孔; 以及在所述第一介电层上的第二电介质层，所述第二介电层包括垂直于所述填充通孔的纵向轴线延伸的沟槽，所述沟槽填充有互连线，所述互连线包含交联的碳纳米管 并且物理地和电连接到填充的通孔。 使用包括前体气体分压大于碳纳米管生长从平行碳纳米管生长模式转变为交联碳的过渡分压的生长条件，将交联的CNT生长在沟槽底部的催化剂颗粒上 纳米管生长模式。

公开(公告)号：US20130228933A1

公开(公告)日：2013-09-05

申请号：US13601963

申请日：2012-08-31

Applicant: Pravin K. Narwankar ,  Joe Griffith Cruz ,  Arvind Sundarrajan ,  Murali Narasimhan ,  Subbalakshmi Sreekala ,  Victor Pushparaj

Inventor： Pravin K. Narwankar ,  Joe Griffith Cruz ,  Arvind Sundarrajan ,  Murali Narasimhan ,  Subbalakshmi Sreekala ,  Victor Pushparaj

IPC: H01L21/768 ,  H01L23/538

CPC classification number: H01L21/76877 ,  A61K8/46 ,  A61K8/8182 ,  A61K2800/884 ,  A61Q9/04 ,  B82Y40/00 ,  H01L21/76843 ,  H01L23/5384 ,  H01L29/413 ,  H01L2924/0002 ,  Y10S977/742 ,  H01L2924/00

Abstract: An integrated circuit with BEOL interconnects may comprise: a substrate including a semiconductor device; a first layer of dielectric over the surface of the substrate, the first layer of dielectric including a filled via for making electrical contact to the semiconductor device; and a second layer of dielectric on the first layer of dielectric, the second layer of dielectric including a trench running perpendicular to the longitudinal axis of the filled via, the trench being filled with an interconnect line, the interconnect line comprising cross-linked carbon nanotubes and being physically and electrically connected to the filled via. Cross-linked CNTs are grown on catalyst particles on the bottom of the trench using growth conditions including a partial pressure of precursor gas greater than the transition partial pressure at which carbon nanotube growth transitions from a parallel carbon nanotube growth mode to a cross-linked carbon nanotube growth mode.

Abstract translation: 具有BEOL互连的集成电路可以包括：包括半导体器件的衬底; 在所述衬底的表面上的第一层电介质，所述第一层电介质包括用于与所述半导体器件电接触的填充通孔; 以及在所述第一介电层上的第二电介质层，所述第二介电层包括垂直于所述填充通孔的纵向轴线延伸的沟槽，所述沟槽填充有互连线，所述互连线包含交联的碳纳米管 并且物理地和电连接到填充的通孔。 使用包括前体气体分压大于碳纳米管生长从平行碳纳米管生长模式转变为交联碳的过渡分压的生长条件，将交联的CNT生长在沟槽底部的催化剂颗粒上 纳米管生长模式。

公开(公告)号：US20130196078A1

公开(公告)日：2013-08-01

申请号：US13754771

申请日：2013-01-30

Applicant: Joseph Yudovsky ,  Nag B. Patibandla ,  Pravin K. Narwankar ,  Li-Qun Xia ,  Toshiaki Fujita ,  Ralf Hofmann ,  Jeonghoon Oh ,  Srinivas Satya ,  Banqiu Wu

Inventor： Joseph Yudovsky ,  Nag B. Patibandla ,  Pravin K. Narwankar ,  Li-Qun Xia ,  Toshiaki Fujita ,  Ralf Hofmann ,  Jeonghoon Oh ,  Srinivas Satya ,  Banqiu Wu

IPC: C23C16/458

CPC classification number: C23C16/4584 ,  C23C16/45519 ,  C23C16/45551 ,  C23C16/54 ,  H01L21/67742

Abstract: A substrate processing system for processing multiple substrates is provided and generally includes at least one substrate processing platform and at least one substrate staging platform. The substrate processing platform includes a rotary track system capable of supporting multiple substrate support assemblies and continuously rotating the substrate support assemblies, each carrying a substrate thereon. Each substrate is positioned on a substrates support assembly disposed on the rotary track system and being processed through at least one shower head station and at least one buffer station, which are positioned atop the rotary track system of the substrate processing platform. Multiple substrates disposed on the substrate support assemblies are processed in and out the substrate processing platform. The substrate staging platform includes at least one dual-substrate processing station, each dual-substrate processing station includes two substrate support assemblies for supporting two substrates thereon.

Abstract translation: 提供了用于处理多个基板的基板处理系统，并且通常包括至少一个基板处理平台和至少一个基板分段平台。 基板处理平台包括能够支撑多个基板支撑组件并且连续旋转基板支撑组件的旋转轨道系统，每个基板支撑组件在其上承载基板。 每个基板定位在设置在旋转轨道系统上的基板支撑组件上，并且通过位于基板处理平台的旋转轨道系统顶部的至少一个喷头站和至少一个缓冲站进行处理。 设置在基板支撑组件上的多个基板在基板处理平台内进出处理。 衬底分级平台包括至少一个双衬底处理站，每个双衬底处理站包括用于在其上支撑两个衬底的两个衬底支撑组件。

公开(公告)号：US08323754B2

公开(公告)日：2012-12-04

申请号：US10851514

申请日：2004-05-21

Applicant: Christopher Olsen ,  Pravin K. Narwankar ,  Shreyas S. Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip A. Kraus

Inventor： Christopher Olsen ,  Pravin K. Narwankar ,  Shreyas S. Kher ,  Randhir Thakur ,  Shankar Muthukrishnan ,  Philip A. Kraus

IPC: H05H1/24

CPC classification number: H01L21/3141 ,  C23C16/401 ,  C23C16/405 ,  C23C16/45529 ,  C23C16/56 ,  H01L21/28202 ,  H01L21/3143 ,  H01L21/31637 ,  H01L21/31645 ,  H01L29/517

Abstract: In one embodiment, a method for forming a dielectric stack on a substrate is provided which includes depositing a first layer of a dielectric material on a substrate surface, exposing the first layer to a nitridation process, depositing a second layer of the dielectric material on the first layer, exposing the second layer to the nitridation process, and exposing the substrate to an anneal process. In another embodiment, a method for forming a dielectric material on a substrate is provided which includes depositing a metal oxide layer substantially free of silicon on a substrate surface, exposing the metal oxide layer to a nitridation process, and exposing the substrate to an anneal process.

Abstract translation: 在一个实施例中，提供了一种在衬底上形成电介质堆叠的方法，其包括在衬底表面上沉积介电材料的第一层，将第一层暴露于氮化工艺，将第二层介电材料沉积在 第一层，将第二层暴露于氮化工艺，并将衬底暴露于退火工艺。 在另一个实施例中，提供了一种用于在衬底上形成介电材料的方法，其包括在衬底表面上沉积基本上不含硅的金属氧化物层，将金属氧化物层暴露于氮化工艺，以及将衬底暴露于退火工艺 。

公开(公告)号：US20100090294A1

公开(公告)日：2010-04-15

申请号：US12641064

申请日：2009-12-17

Applicant: Pravin K. Narwankar ,  Gary E. Miner ,  Arnaud Lepert

Inventor： Pravin K. Narwankar ,  Gary E. Miner ,  Arnaud Lepert

IPC: H01L29/78 ,  B32B5/00 ,  C04B35/14 ,  C04B35/597

CPC classification number: H01L21/02332 ,  H01L21/0214 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/3105 ,  H01L21/3144 ,  H01L29/518 ,  H01L29/66181

Abstract: A method of forming a dielectric film that includes nitrogen. The method includes incorporating nitrogen into a dielectric film using a nitridation gas and a rapid thermal annealing process, wherein an ultra-low pressure of equal to or less than about 10 Torr is used for the rapid thermal annealing process.

Abstract translation: 一种形成包括氮的电介质膜的方法。 该方法包括使用氮化气体和快速热退火工艺将氮合并到电介质膜中，其中使用等于或小于约10Torr的超低压用于快速热退火工艺。

公开(公告)号：US20080099933A1

公开(公告)日：2008-05-01

申请号：US11554954

申请日：2006-10-31

Applicant: Kenric T. Choi ,  Pravin K. Narwankar ,  Shreyas S. Kher ,  Son T. Nguyen ,  Paul Deaton ,  Khai Ngo ,  Paul Chhabra ,  Alan H. Ouye ,  Dien-Yeh (Daniel) Wu

Inventor： Kenric T. Choi ,  Pravin K. Narwankar ,  Shreyas S. Kher ,  Son T. Nguyen ,  Paul Deaton ,  Khai Ngo ,  Paul Chhabra ,  Alan H. Ouye ,  Dien-Yeh (Daniel) Wu

IPC: F16K13/00 ,  B01F3/04

CPC classification number: C23C16/4481

Abstract: A method and apparatus for providing a precursor to a process chamber is described. The apparatus comprises an ampoule capable of receiving either a liquid precursor source material or a solid precursor source material. The ampoule is capable of delivering either a liquid precursor material to a vaporizer coupled to the process chamber, or a vaporized or gaseous precursor material to the process chamber. The ampoule also includes a continuous level sensor to accurately monitor the level of precursor source material within the ampoule.

Abstract translation: 描述了一种用于向处理室提供前体的方法和装置。 该装置包括能够接收液体前体源材料或固体前体源材料的安瓿。 安瓿能够将液体前体材料输送到耦合到处理室的蒸发器，或将蒸发的或气态的前体材料输送到处理室。 安瓿还包括连续液位传感器，以准确地监测安瓿内的前体源材料的含量。

公开(公告)号：US06573150B1

公开(公告)日：2003-06-03

申请号：US09686451

申请日：2000-10-10

Applicant: Randall S. Urdahl ,  Pravin K. Narwankar ,  Shankarrram A. Athreya ,  Asher K. Sinensky ,  Andrea M. Mendoza

Inventor： Randall S. Urdahl ,  Pravin K. Narwankar ,  Shankarrram A. Athreya ,  Asher K. Sinensky ,  Andrea M. Mendoza

IPC: H01L2120

CPC classification number: H01L28/75 ,  H01L21/28568 ,  H01L21/31604 ,  H01L28/40 ,  Y10S438/907

Abstract: The present invention provides a method of integrating tantalum oxide into an MIM capacitor for a semiconductor device, comprising the step of vapor-depositing the tantalum oxide from an oxygen-free liquid precursor and under process conditions comprising a deposition temperature of less than about 500° C. and a deposition pressure of less than about 96 Torr, wherein the tantalum oxide is integrated into the MIM capacitor. Also provided is a method of forming an MIM capacitor comprising the step of integrating a tantalum oxide dielectric film with a tantalum nitride or a titanium nitride bottom electrode deposited on a substrate and a titanium nitride top electrode thereby forming an MIM capacitor.

Abstract translation: 本发明提供了一种将钽氧化物整合到用于半导体器件的MIM电容器中的方法，包括从无氧液体前体气相沉积氧化钽的步骤，并且在包括小于约500°的沉积温度的工艺条件下 并且小于约96托的沉积压力，其中所述氧化钽被集成到所述MIM电容器中。 还提供了一种形成MIM电容器的方法，包括将钽氧化物电介质膜与沉积在衬底上的氮化钽或氮化钛底电极和氮化钛上电极集成的步骤，从而形成MIM电容器。