Atomic layer deposition processes for non-volatile memory devices
    6.
    发明授权
    Atomic layer deposition processes for non-volatile memory devices 失效
    用于非易失性存储器件的原子层沉积工艺

    公开(公告)号:US08043907B2

    公开(公告)日:2011-10-25

    申请号:US12687732

    申请日:2010-01-14

    IPC分类号: H01L21/8238

    摘要: Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.

    摘要翻译: 本发明的实施例提供了用于形成这种存储器件的存储器件和方法。 在一个实施例中,提供了一种用于在衬底上制造非易失性存储器件的方法,其包括在衬底表面上沉积第一多晶硅层,在第一多晶硅层上沉积氧化硅层,在第一多晶硅层上沉积第一氧氮化硅层 氧化硅层,在第一氧氮化硅层上沉积氮化硅层,在氮化硅层上沉积第二氮氧化硅层,以及在第二氮氧化硅层上沉积第二多晶硅层。 在一些示例中,第一多晶硅层是浮置栅极,第二多晶硅层是控制栅极。

    Atomic Layer Deposition Processes for Non-Volatile Memory Devices
    7.
    发明申请
    Atomic Layer Deposition Processes for Non-Volatile Memory Devices 失效
    非易失性存储器件的原子层沉积工艺

    公开(公告)号:US20100102376A1

    公开(公告)日:2010-04-29

    申请号:US12687732

    申请日:2010-01-14

    IPC分类号: H01L29/788 H01L21/336

    摘要: Embodiments of the invention provide memory devices and methods for forming such memory devices. In one embodiment, a method for fabricating a non-volatile memory device on a substrate is provided which includes depositing a first polysilicon layer on a substrate surface, depositing a silicon oxide layer on the first polysilicon layer, depositing a first silicon oxynitride layer on the silicon oxide layer, depositing a silicon nitride layer on the first silicon oxynitride layer, depositing a second silicon oxynitride layer on the silicon nitride layer, and depositing a second polysilicon layer on the second silicon oxynitride layer. In some examples, the first polysilicon layer is a floating gate and the second polysilicon layer is a control gate.

    摘要翻译: 本发明的实施例提供了用于形成这种存储器件的存储器件和方法。 在一个实施例中,提供了一种用于在衬底上制造非易失性存储器件的方法,其包括在衬底表面上沉积第一多晶硅层,在第一多晶硅层上沉积氧化硅层,在第一多晶硅层上沉积第一氧氮化硅层 氧化硅层,在第一氧氮化硅层上沉积氮化硅层,在氮化硅层上沉积第二氮氧化硅层,以及在第二氮氧化硅层上沉积第二多晶硅层。 在一些示例中,第一多晶硅层是浮置栅极,第二多晶硅层是控制栅极。

    ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES
    8.
    发明申请
    ATOMIC LAYER DEPOSITION PROCESSES FOR NON-VOLATILE MEMORY DEVICES 失效
    用于非易失性存储器件的原子层沉积工艺

    公开(公告)号:US20090242957A1

    公开(公告)日:2009-10-01

    申请号:US12059782

    申请日:2008-03-31

    IPC分类号: H01L21/28 H01L29/788

    摘要: Embodiments of the invention provide memory devices and methods for forming memory devices. In one embodiment, a memory device is provided which includes a floating gate polysilicon layer disposed over source/drain regions of a substrate, a silicon oxynitride layer disposed over the floating gate polysilicon layer, a first aluminum oxide layer disposed over the silicon oxynitride layer, a hafnium silicon oxynitride layer disposed over the first aluminum oxide layer, a second aluminum oxide layer disposed over the hafnium silicon oxynitride layer, and a control gate polysilicon layer disposed over the second aluminum oxide layer. In another embodiment, a memory device is provided which includes a control gate polysilicon layer disposed over an inter-poly dielectric stack disposed over a silicon oxide layer disposed over the floating gate polysilicon layer. The inter-poly dielectric stack contains two silicon oxynitride layers separated by a silicon nitride layer.

    摘要翻译: 本发明的实施例提供了用于形成存储器件的存储器件和方法。 在一个实施例中,提供了一种存储器件,其包括设置在衬底的源极/漏极区域上的浮置栅极多晶硅层,设置在浮置栅极多晶硅层上的氧氮化硅层,设置在氧氮化硅层上的第一氧化铝层, 设置在所述第一氧化铝层上的铪硅氮化物层,设置在所述铪硅氮氧化物层上的第二氧化铝层,以及设置在所述第二氧化铝层上的控制栅极多晶硅层。 在另一个实施例中,提供了一种存储器件,其包括设置在布置在浮置多晶硅层上方的氧化硅层上的多晶硅介质叠层之间的控制栅极多晶硅层。 多晶硅间介质堆叠包含由氮化硅层分隔的两个氮氧化硅层。

    Method of synthesizing III-V semiconductor nanocrystals
    10.
    发明授权
    Method of synthesizing III-V semiconductor nanocrystals 失效
    合成III-V族半导体纳米晶体的方法

    公开(公告)号:US5474591A

    公开(公告)日:1995-12-12

    申请号:US189232

    申请日:1994-01-31

    摘要: The present invention relates, in general, to a method of synthesizing nanocrystals and, in particular, to a method of synthesizing III-V semiconductor nanocrystals in solution at a low temperature and in a high yield. The method comprises the combination of mixing a Na/K alloy with an excess of Group VA element (E) in an aromatic solvent to form a (Na/K).sub.3 E pnictide, and subsequently mixing the pnictide with a Group IIIA trihalide (MX.sub.3) in a coordinating solution to form a suspension that includes the nanocrystalline semiconductor.

    摘要翻译: 本发明一般涉及一种合成纳米晶体的方法,尤其涉及在低温和高收率下在溶液中合成III-V族半导体纳米晶体的方法。 该方法包括将Na / K合金与过量的VA族元素(E)在芳族溶剂中混合以形成(Na / K)3E pnictide,然后将该混合物与IIIA族三卤化物(MX3)混合, 在协调解决方案中形成包括纳米晶体半导体的悬浮液。