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    Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile
    22.
    发明授权
    Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile 有权
    用于均匀氮分布的超薄二氧化硅层的氨退火方法

    公开(公告)号：US06632747B2

    公开(公告)日：2003-10-14

    申请号：US09885600

    申请日：2001-06-20

    申请人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

    发明人： Hiroaki Niimi ,  Douglas T. Grider ,  Rajesh Khamankar ,  Sunil Hattangady

    IPC分类号： H01L2131

    CPC分类号： H01L21/02332 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

    摘要： An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C. for 5 to 60 s); annealing in an oxidizer/hydrogen mixture (preferably N2O with 1% H2) for 5 to 60 s at 800 to 1050° C.

    摘要翻译： 本发明的一个实施例是通过提供具有半导体表面的衬底来形成超薄电介质层的方法; 在半导体表面上形成含氧层; 将含氧层暴露于含氮等离子体以在整个含氧层中产生均匀的氮分布; 并重新氧化和退火该层以稳定氮分布，治愈等离子体诱导的损伤并降低界面缺陷密度。该退火步骤选自一组四种再氧化技术：连续 在H 2和N 2（优选小于20％H 2）的混合物中进行退火，然后将O 2和N 2（优选小于20％的O 2）的混合物进行退火;通过尖峰状温度升高（优选小于20％ （优选为N 2 / O 2或N 2 O / H 2）;通过在减压下的氨中快速热加热（优选在600至1000℃下，对于 5至60秒）;在800至1050℃下在氧化剂/氢气混合物（优选N 2 O与1％H 2）中退火5至60秒。

    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device
    23.
    发明授权
    Substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant forming P-LDD region of a PMOS device 失效
    具有受控量的惰性气体离子的衬底，以减少形成PMOS器件的P-LDD区域的硼掺杂物的沟道和/或扩散

    公开(公告)号：US5717238A

    公开(公告)日：1998-02-10

    申请号：US677078

    申请日：1996-07-09

    申请人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    发明人： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

    IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

    CPC分类号： H01L29/6659 ,  H01L21/26506

    摘要： A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

    摘要翻译： 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

    POLYCRYSTALLINE SILICON EFUSE AND RESISTOR FABRICATION IN A METAL REPLACEMENT GATE PROCESS
    24.
    发明申请
    POLYCRYSTALLINE SILICON EFUSE AND RESISTOR FABRICATION IN A METAL REPLACEMENT GATE PROCESS 审中-公开
    金属替代浇口工艺中的多晶硅膜和电阻器制造

    公开(公告)号：US20140011333A1

    公开(公告)日：2014-01-09

    申请号：US13544354

    申请日：2012-07-09

    申请人： Benjamin P. McKee ,  Yongqiang Jiang ,  Douglas T. Grider

    发明人： Benjamin P. McKee ,  Yongqiang Jiang ,  Douglas T. Grider

    IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/02

    CPC分类号： H01L21/823842 ,  H01L21/28123 ,  H01L23/5256 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of fabricating an integrated circuit is disclosed (FIGS. 1-2). The method comprises providing a substrate (200) having an isolation region (202) and etching a trench in the isolation region. A first conductive layer (214) is formed within the trench. A first transistor having a first conductivity type (n-channel) is formed at a face of the substrate. The first transistor has a gate (216) formed of the first conductive layer. A second transistor having a second conductivity type (p-channel) is formed at the face of the substrate. The second transistor has a gate (224) formed of the first conductive layer. The method further comprises replacing the first conductive layer of the first transistor with a first metal gate (132) and replacing the first conductive layer of the second transistor with a second metal gate (134).

    摘要翻译： 公开了一种制造集成电路的方法（图1-2）。 该方法包括提供具有隔离区域（202）并蚀刻隔离区域中的沟槽的衬底（200）。 第一导电层（214）形成在沟槽内。 具有第一导电类型（n沟道）的第一晶体管形成在衬底的表面。 第一晶体管具有由第一导电层形成的栅极（216）。 在衬底的表面形成具有第二导电类型（p沟道）的第二晶体管。 第二晶体管具有由第一导电层形成的栅极（224）。 该方法还包括用第一金属栅极（132）代替第一晶体管的第一导电层，并用第二金属栅极（134）代替第二晶体管的第一导电层。

    Nitrogen based implants for defect reduction in strained silicon
    25.
    发明授权
    Nitrogen based implants for defect reduction in strained silicon 有权
    用于应变硅缺陷还原的氮基植入物

    公开(公告)号：US08084312B2

    公开(公告)日：2011-12-27

    申请号：US12688442

    申请日：2010-01-15

    申请人： Srinivasan Chakravarthi ,  P R Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

    发明人： Srinivasan Chakravarthi ,  P R Chidambaram ,  Rajesh Khamankar ,  Haowen Bu ,  Douglas T. Grider

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7843

    摘要： A transistor is fabricated upon a semiconductor substrate, where the yield strength or elasticity of the substrate is enhanced or otherwise adapted. A strain inducing layer is formed over the transistor to apply a strain thereto to alter transistor operating characteristics, and more particularly to enhance the mobility of carriers within the transistor. Enhancing carrier mobility allows transistor dimensions to be reduced while also allowing the transistor to operate as desired. However, high strain and temperature associated with fabricating the transistor result in deleterious plastic deformation. The yield strength of the silicon substrate is therefore adapted by incorporating nitrogen into the substrate, and more particularly into source/drain extension regions and/or source/drain regions of the transistor. The nitrogen can be readily incorporated during transistor fabrication by adding it as part of source/drain extension region formation and/or source/drain region formation. The enhanced yield strength of the substrate mitigates plastic deformation of the transistor due to the strain inducing layer.

    摘要翻译： 晶体管制造在半导体衬底上，其中衬底的屈服强度或弹性得到增强或适应。 应变感应层形成在晶体管上以向其施加应变以改变晶体管工作特性，更具体地说，增强晶体管内的载流子迁移率。 增强载流子迁移率允许晶体管尺寸减小，同时也允许晶体管根据需要进行操作。 然而，与制造晶体管相关的高应变和温度导致有害的塑性变形。 因此，硅衬底的屈服强度通过将氮掺入到衬底中，更具体地掺入晶体管的源极/漏极延伸区域和/或源极/漏极区域来适应。 在晶体管制造期间，可以通过将其作为源极/漏极延伸区域形成和/或源极/漏极区域形成的一部分来添加来将氮容易地并入。 由于应变诱导层，衬底的增强的屈服强度减轻了晶体管的塑性变形。

    PMD liner nitride films and fabrication methods for improved NMOS performance
    26.
    发明授权
    PMD liner nitride films and fabrication methods for improved NMOS performance 有权
    PMD衬垫氮化物膜和用于改善NMOS性能的制造方法

    公开(公告)号：US07226834B2

    公开(公告)日：2007-06-05

    申请号：US10827692

    申请日：2004-04-19

    申请人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    发明人： Haowen Bu ,  Rajesh Khamankar ,  Douglas T. Grider

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/823807 ,  H01L29/665 ,  Y10S438/938

    摘要： Semiconductor devices (102) and fabrication methods (10) are provided, in which a nitride film (130) is formed over NMOS transistors to impart a tensile stress in all or a portion of the NMOS transistor to improve carrier mobility. The nitride layer (130) is initially deposited over the transistors at low temperature with high hydrogen content to provide a moderate tensile stress in the semiconductor body prior to back-end processing. Subsequent back-end thermal processing reduces the film hydrogen content and causes an increase in the applied tensile stress.

    摘要翻译： 提供半导体器件（102）和制造方法（10），其中在NMOS晶体管上形成氮化物膜（130）以在NMOS晶体管的全部或一部分中施加拉伸应力以改善载流子迁移率。 氮化物层（130）最初以高氢含量在低温下沉积在晶体管上，以在后端处理之前在半导体本体中提供适度的拉伸应力。 随后的后端热处理降低了膜的氢含量并且引起所施加的拉伸应力的增加。

    Semiconductor device isolation structure and method of forming
    28.
    发明授权
    Semiconductor device isolation structure and method of forming 有权
    半导体器件隔离结构及其形成方法

    公开(公告)号：US06737333B2

    公开(公告)日：2004-05-18

    申请号：US10176383

    申请日：2002-06-20

    申请人： Zhihao Chen ,  Douglas T. Grider ,  Freidoon Mehrad

    发明人： Zhihao Chen ,  Douglas T. Grider ,  Freidoon Mehrad

    IPC分类号： H01L2176

    CPC分类号： H01L21/76224

    摘要： A method for isolating semiconductor devices includes forming a first oxide layer outwardly from a semiconductor substrate, forming a first nitride layer outwardly from the first oxide layer, removing a portion of the first nitride layer, a portion of the first oxide layer, and a portion of the substrate to form a trench isolation region, forming a second oxide layer in the trench isolation region, forming a spin-on-glass region in the trench isolation region, annealing the spin-on-glass region, removing a portion of the spin-on-glass region to expose a shallow trench isolation region, and forming a third oxide layer in the shallow trench isolation region.

    摘要翻译： 隔离半导体器件的方法包括从半导体衬底向外形成第一氧化物层，从第一氧化物层向外形成第一氮化物层，去除第一氮化物层的一部分，第一氧化物层的一部分，以及部分 以形成沟槽隔离区域，在沟槽隔离区域中形成第二氧化物层，在沟槽隔离区域中形成旋涂玻璃区域，退火玻璃转移区域，去除部分旋转 以暴露浅沟槽隔离区域，并且在浅沟槽隔离区域中形成第三氧化物层。