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21.发明授权Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法公开(公告)号：US07879660B2
公开(公告)日：2011-02-01
申请号：US11927780
申请日：2007-10-30
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷并且至少部分地用介电材料填充凹部。
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22.发明授权Design structures incorporating interconnect structures with liner repair layers 有权设计结构包括具有衬里修复层的互连结构公开(公告)号：US07494916B2
公开(公告)日：2009-02-24
申请号：US11875345
申请日：2007-10-19
IPC分类号： H01L21/4763
CPC分类号： H01L23/53238 , H01L21/76814 , H01L21/76844 , H01L21/76846 , H01L21/76868 , H01L2924/0002 , H01L2924/00
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes an interconnect structure with a liner formed on roughened dielectric material in an insulating layer and a conformal liner repair layer bridging that breaches in the liner. The conformal liner repair layer is formed of a conductive material, such as a cobalt-containing material. The conformal liner repair layer may be particularly useful for repairing discontinuities in a conductive liner disposed on roughened dielectric material bordering the trenches and vias of damascene interconnect structures.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括互连结构，其具有在绝缘层中的粗糙化介电材料上形成的衬垫和桥接该衬里中的破损的保形衬里修复层。 保形衬里修复层由诸如含钴材料的导电材料形成。 保形衬里修复层可能特别适用于修复布置在与镶嵌互连结构的沟槽和通孔相邻的粗糙化介电材料上的导电衬垫中的不连续性。
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23.发明申请公开(公告)号：US20090007037A1
公开(公告)日：2009-01-01
申请号：US11925413
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/28052 , H01L21/28097 , H01L21/823443 , H01L21/82345 , H01L21/823475 , H01L21/823835 , H01L21/823842 , H01L21/823871 , H01L28/20 , H01L29/4933 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices and more specifically to forming partially silicided and fully silicided structures. Fabricating the partially silicided and fully silicided structures may involve creating one or more gate stacks. A polysilicon layer of a first gate stack may be exposed and a first metal layer may be deposited thereon to create a partially silicided structure. Thereafter, a polysilicon layer of a second gate stack may be exposed and a second metal layer may be deposited thereon to form a fully silicided structure. In some embodiments, the polysilicon layers of one or more gate stacks may not be exposed, and resistors may be formed with the unsilicided polysilicon layers.
摘要翻译： 本发明的实施例一般涉及用于半导体器件的方法，系统和设计结构，更具体地涉及形成部分硅化和完全硅化结构。 制造部分硅化和完全硅化的结构可能涉及创建一个或多个栅极叠层。 可以暴露第一栅极叠层的多晶硅层，并且可以在其上沉积第一金属层以产生部分硅化结构。 此后，可以暴露第二栅极堆叠的多晶硅层，并且可以在其上沉积第二金属层以形成完全硅化的结构。 在一些实施例中，可以不暴露一个或多个栅极叠层的多晶硅层，并且可以用非硅化多晶硅层形成电阻器。
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公开(公告)号：US20090007036A1
公开(公告)日：2009-01-01
申请号：US11925387
申请日：2007-10-26
IPC分类号： G06F9/45
CPC分类号： H01L21/845 , H01L27/1211 , H01L29/41791 , H01L29/66795 , H01L29/785 , H01L2029/7858
摘要： Embodiments of the invention generally relate to methods, systems and design structures for semiconductor devices, and more specifically to interconnecting semiconductor devices. A silicide layer may be formed on selective areas of a fin structure connecting one or more semiconductor devices or semiconductor device components. By providing silicided fin structures to locally interconnect semiconductor devices, the use of metal contacts and metal layers may be obviated, thereby allowing formation of smaller, less complex circuits.
摘要翻译： 本发明的实施例一般涉及半导体器件的方法，系统和设计结构，更具体地涉及互连半导体器件。 可以在连接一个或多个半导体器件或半导体器件部件的翅片结构的选择性区域上形成硅化物层。 通过提供硅化物翅片结构来局部互连半导体器件，可以避免使用金属触点和金属层，从而形成较小的，较不复杂的电路。
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25.发明申请公开(公告)号：US20080120580A1
公开(公告)日：2008-05-22
申请号：US11875193
申请日：2007-10-19
IPC分类号： G06F17/50
CPC分类号： H01L21/76834 , H01L21/76849 , H01L21/76883 , H01L21/76885
摘要： Design structure embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure comprises an insulating layer of a dielectric material, an opening having sidewalls extending from a top surface of the insulating layer toward a bottom surface of the insulating layer, and a conductive feature disposed in the opening. The design structure includes a top capping layer disposed on at least a top surface of the conductive feature and a conductive liner layer disposed between the insulating layer and the conductive feature along at least the sidewalls of the opening. The conductive liner layer of the design structure has sidewall portions that project above the top surface of the insulating layer adjacent to the sidewalls of the opening.
摘要翻译： 用于设计，制造或测试设计的机器可读介质中体现的设计结构。 该设计结构包括介电材料的绝缘层，具有从绝缘层的顶表面朝向绝缘层的底表面延伸的侧壁的开口以及设置在该开口中的导电特征。 该设计结构包括设置在导电特征的至少顶表面上的顶盖层和至少沿开口的侧壁设置在绝缘层和导电特征之间的导电衬垫层。 该设计结构的导电衬里层具有侧壁部分，该侧壁部分突出在邻近开口侧壁的绝缘层顶表面上方。
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26.发明授权Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates 失效用于形成这种混合取向基板的混合取向基板和晶体压印方法公开(公告)号：US07875960B2
公开(公告)日：2011-01-25
申请号：US12182560
申请日：2008-07-30
IPC分类号： H01L29/04
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/045
摘要： A semiconductor structure with an insulating layer on a silicon substrate, a plurality of electrically-isolated silicon-on-insulator (SOI) regions separated from the substrate by the insulating layer, and a plurality of electrically-isolated silicon bulk regions extending through the insulating layer to the substrate. Each of one number of the SOI regions is oriented with a first crystal orientation and each of another number of the SOI regions is oriented with a second crystal orientation that differs from the first crystal orientation. The bulk silicon regions are each oriented with a third crystal orientation. Damascene or imprinting methods of forming the SOI regions and bulk silicon regions are also provided.
摘要翻译： 一种在硅衬底上具有绝缘层的半导体结构，通过绝缘层从衬底分离出的多个电隔离绝缘体上硅（SOI）区域，以及延伸穿过绝缘体的多个电隔离硅体区域 层到基底。 SOI区域中的每一个以第一晶体取向取向，并且另外数量的SOI区域中的每一个以与第一晶体取向不同的第二晶体取向取向。 体硅区域各自定向为具有第三晶体取向。 还提供了形成SOI区域和体硅区域的镶嵌或印记方法。
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公开(公告)号：US20100320563A1
公开(公告)日：2010-12-23
申请号：US12870921
申请日：2010-08-30
IPC分类号： H01L23/525
CPC分类号： H01L23/5256 , H01L21/76807 , H01L21/76892 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： A structure. The structure includes: a substrate; a first electrode in the substrate; a dielectric layer on top of the substrate and the electrode; a second dielectric layer on the first dielectric layer, said second dielectric layer comprising a second dielectric material; a fuse element buried in the first dielectric layer, wherein the fuse element (i) physically separates, (ii) is in direct physical contact with both, and (iii) is sandwiched between a first region and a second region of the dielectric layer; and a second electrode on top of the fuse element, wherein the first electrode and the second electrode are electrically coupled to each other through the fuse element.
摘要翻译： 一个结构。 该结构包括：基底; 衬底中的第一电极; 在所述基板和所述电极的顶部上的介电层; 在所述第一介电层上的第二电介质层，所述第二电介质层包括第二电介质材料; 埋入第一介电层中的熔丝元件，其中熔融元件（i）物理分离，（ii）与二者直接物理接触，（iii）被夹在介电层的第一区域和第二区域之间; 以及在所述熔丝元件的顶部上的第二电极，其中所述第一电极和所述第二电极通过所述熔丝元件彼此电耦合。
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28.发明授权Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法公开(公告)号：US07692250B2
公开(公告)日：2010-04-06
申请号：US11927110
申请日：2007-10-29
IPC分类号： H01L27/12
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach, and semiconductor structures formed by the methods. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译： 通过镶嵌法在公共衬底上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法以及通过该方法形成的半导体结构。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。
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29.发明授权Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures 有权将镶嵌体FinFET和平面器件集成在共同衬底上的半导体结构以及用于形成这种半导体结构的方法公开(公告)号：US07352034B2
公开(公告)日：2008-04-01
申请号：US11211956
申请日：2005-08-25
IPC分类号： H01L29/94
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823821 , H01L21/823828 , H01L21/82385 , H01L21/823878 , H01L21/845 , H01L27/0924 , H01L27/1211 , H01L29/66795 , H01L29/785
摘要： Methods of forming a semiconductor structure having FinFET's and planar devices, such as MOSFET's, on a common substrate by a damascene approach. A semiconductor fin of the FinFET is formed on a substrate with damascene processing in which the fin growth may be interrupted to implant ions that are subsequently transformed into a region that electrically isolates the fin from the substrate. The isolation region is self-aligned with the fin because the mask used to form the damascene-body fin also serves as an implantation mask for the implanted ions. The fin may be supported by the patterned layer during processing that forms the FinFET and, more specifically, the gate of the FinFET. The electrical isolation surrounding the FinFET may also be supplied by a self-aligned process that recesses the substrate about the FinFET and at least partially fills the recess with a dielectric material.
摘要翻译： 通过大马士革方法在公共基板上形成具有FinFET和诸如MOSFET的平面器件的半导体结构的方法。 FinFET的半导体鳍形成在具有镶嵌处理的衬底上，其中翅片生长可以被中断以注入离子，随后将其转换成将鳍片与衬底电隔离的区域。 隔离区域与翅片自对准，因为用于形成镶嵌体体翅片的掩模也用作注入离子的注入掩模。 翅片可以在形成FinFET的处理期间由图案化层支撑，更具体地，FinFET的栅极支撑。 围绕FinFET的电隔离也可以通过自对准工艺来提供，该工艺使得衬底围绕FinFET凹陷，并且用电介质材料至少部分地填充凹部。
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公开(公告)号：US07276775B2
公开(公告)日：2007-10-02
申请号：US10329593
申请日：2002-12-26
申请人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
发明人： Claude Louis Bertin , Anthony J. Dally , John Atkinson Fifield , John Jesse Higgins , Jack Allan Mandelman , William Robert Tonti , Nicholas Martin van Heel
IPC分类号： H01L29/04 , H01L31/036 , H01L27/10 , H01L29/00
CPC分类号： H01L21/2822 , H01L21/2255 , H01L21/26506 , H01L21/26533 , H01L21/28238 , H01L21/823462 , H01L29/42368 , H01L29/511 , H01L29/6653 , H01L29/66553 , H01L29/66583 , H01L29/66613 , H01L29/7834
摘要： Damascene or non-damascene processing when used with a method that includes (a) forming a mask having an opening therethrough on a structure, said opening having sidewalls; (b) implanting an inhibiting species into said structure through the opening so as to form an inhibiting region in said structure; and (c) growing a dielectric layer on the structure in said opening, wherein the inhibiting region partially inhibits growth of the dielectric layer is capable of forming a semiconductor structure, e.g., MOSFET or anti-fuse, including a dual thickness dielectric layer. Alternatively, the dual thickness dielectric can be formed by replacing the inhibiting species mentioned above with a dielectric growth enhancement species which forms an enhancing region in the structure which aids in the growth of the dielectric layer.
摘要翻译： 当与包括（a）在结构上形成具有开口的掩模的方法一起使用时，镶嵌或非镶嵌加工，所述开口具有侧壁; （b）通过开口将抑制物质注入所述结构中，以在所述结构中形成抑制区域; 和（c）在所述开口中的结构上生长电介质层，其中抑制区域部分抑制电介质层的生长能够形成半导体结构，例如包括双重厚度介电层的MOSFET或反熔丝。 或者，可以通过用有助于电介质层生长的结构中形成增强区的介电生长增强物种代替上述抑制物质来形成双重厚度电介质。
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