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    Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same
    21.
    发明授权
    Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same 有权
    包括具有三维通道的晶体管的半导体器件及其制造方法

    公开(公告)号：US07432160B2

    公开(公告)日：2008-10-07

    申请号：US11699301

    申请日：2007-01-29

    申请人： Eun-Suk Cho ,  Chul Lee

    发明人： Eun-Suk Cho ,  Chul Lee

    IPC分类号： H01L21/336 ,  H01L21/8234

    CPC分类号： H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

    Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same
    22.
    发明申请
    Semiconductor devices including transistors having three dimensional channels and methods of fabricating the same 有权
    包括具有三维通道的晶体管的半导体器件及其制造方法

    公开(公告)号：US20070184627A1

    公开(公告)日：2007-08-09

    申请号：US11699301

    申请日：2007-01-29

    申请人： Eun-Suk Cho ,  Chul Lee

    发明人： Eun-Suk Cho ,  Chul Lee

    IPC分类号： H01L21/20

    CPC分类号： H01L23/485 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/7854 ,  H01L2029/7858 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Semiconductor devices including a gate electrode crossing over a semiconductor fin on a semiconductor substrate are provided. A gate insulating layer is provided between the gate electrode and the semiconductor fin. A channel region having a three-dimensional structure defined at the semiconductor fin under the gate electrode is also provided. Doped region is provided in the semiconductor fin at either side of the gate electrode and an interlayer insulating layer is provided on a surface of the semiconductor substrate. A connector region is coupled to the doped region and provided in an opening, which penetrates the interlayer insulating layer. A recess region is provided in the doped region and is coupled to the connector region. The connector region contacts an inner surface of the recess region. Related methods of fabricating semiconductor devices are also provided herein.

    摘要翻译： 提供包括在半导体衬底上与半导体鳍状物交叉的栅电极的半导体器件。 栅极绝缘层设置在栅电极和半导体鳍之间。 还提供了在栅电极下方的半导体鳍片处限定的具有三维结构的沟道区域。 掺杂区域设置在栅电极的任一侧的半导体鳍片中，并且在半导体衬底的表面上设置层间绝缘层。 连接器区域耦合到掺杂区域并且设置在穿过层间绝缘层的开口中。 在掺杂区域中提供凹陷区域并且耦合到连接器区域。 连接器区域接触凹部区域的内表面。 本文还提供了制造半导体器件的相关方法。

    Method of operating a flash memory device
    24.
    发明申请
    Method of operating a flash memory device 失效
    操作闪存设备的方法

    公开(公告)号：US20060104116A1

    公开(公告)日：2006-05-18

    申请号：US11274310

    申请日：2005-11-16

    申请人： Jae-Man Yoon ,  Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee

    发明人： Jae-Man Yoon ,  Eun-Suk Cho ,  Dong-Gun Park ,  Choong-Ho Lee

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： A method of operating a NAND flash memory device that comprising a unit string comprising a string selection transistor connected to a bit line, a cell transistor connected to the string selection transistor, and a ground selection transistor connected to the cell transistor is provided. The method comprises applying a negative bias voltage to the string selection transistor and the ground selection transistor in a stand-by mode of the NAND flash memory device.

    摘要翻译： 提供一种操作NAND闪速存储器件的方法，该NAND闪速存储器件包括连接到位线的串选择晶体管，连接到串选择晶体管的单元晶体管和连接到单元晶体管的接地选择晶体管的单元串。 该方法包括在NAND闪速存储器件的待机模式中向串选择晶体管和接地选择晶体管施加负偏置电压。

    Reformer and fuel cell system having the same
    25.
    发明申请
    Reformer and fuel cell system having the same 审中-公开
    重整器和燃料电池系统具有相同的功能

    公开(公告)号：US20060014056A1

    公开(公告)日：2006-01-19

    申请号：US11165618

    申请日：2005-06-22

    申请人： Zin Park ,  Ju-Yong Kim ,  Ji-Seong Han ,  Hyun-Jeong Lim ,  Eun-Suk Cho ,  Ho-Jin Kweon ,  Bok-Hwan Jung

    发明人： Zin Park ,  Ju-Yong Kim ,  Ji-Seong Han ,  Hyun-Jeong Lim ,  Eun-Suk Cho ,  Ho-Jin Kweon ,  Bok-Hwan Jung

    IPC分类号： H01M8/00 ,  B01J7/00

    CPC分类号： C01B3/38 ,  B01J12/007 ,  B01J19/249 ,  B01J2219/00135 ,  B01J2219/00155 ,  B01J2219/2459 ,  B01J2219/2467 ,  B01J2219/2479 ,  B01J2219/2485 ,  B01J2219/2496 ,  C01B2203/0227 ,  C01B2203/066 ,  C01B2203/085 ,  H01M8/0618 ,  H01M8/0631

    摘要： A fuel cell system comprises a reformer for generating hydrogen from fuel, at least one electricity generator for generating electric energy through an electrochemical reaction between hydrogen and oxygen, a fuel supply unit for supplying the fuel to the reformer and an oxygen supply unit for supplying oxygen to the electricity generator. The reformer includes a main body which has an inner space with a reformer inlet and a reformer outlet. A reaction section is disposed within the inner space of the main body. The reaction section includes a heat-generating element for generating thermal energy from externally applied energy such as electrical current. The heat-generating element has a corrugated structure with a catalyst layer formed on the surface. The corrugated structure defines a plurality of flow passages for the fuel and encourages both even flow distribution and turbulent flow.

    摘要翻译： 燃料电池系统包括用于从燃料产生氢的重整器，用于通过氢和氧之间的电化学反应产生电能的至少一个发电机，用于向重整器供应燃料的燃料供应单元和用于供应氧气的氧气供应单元 发电机。 重整器包括具有重整器入口和重整器出口的内部空间的主体。 反应部设置在主体的内部空间内。 反应部分包括用于从诸如电流的外部施加的能量产生热能的发热元件。 发热元件具有在表面上形成有催化剂层的波纹结构。 波纹结构限定了用于燃料的多个流动通道并且促进均匀的流量分布和湍流。

    Isolation method of defining active fins, method of fabricating semiconductor device using the same and semiconductor device fabricated thereby
    30.
    发明申请
    Isolation method of defining active fins, method of fabricating semiconductor device using the same and semiconductor device fabricated thereby 审中-公开
    限定活性鳍片的隔离方法，使用其制造半导体器件的方法以及由此制造的半导体器件

    公开(公告)号：US20070134884A1

    公开(公告)日：2007-06-14

    申请号：US11488584

    申请日：2006-07-18

    申请人： Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

    发明人： Keun-Nam Kim ,  Chul Lee ,  Eun-Suk Cho

    IPC分类号： H01L21/76 ,  H01L29/00 ,  H01L21/4763

    CPC分类号： H01L21/823437 ,  H01L21/823481 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/7851

    摘要： An isolation method of defining active fins, a method of fabricating a semiconductor device using the same, and a semiconductor device fabricated thereby are provided. The method of fabricating a semiconductor device includes: preparing a semiconductor substrate; and forming a plurality of active fins having major and minor axes and two-dimensionally arrayed on the semiconductor substrate in directions of the major and minor axes. A liner pattern is formed on lower sidewalls of the active fins. An isolation layer is formed on the semiconductor substrate having the liner pattern, and the isolation layer exposes top surfaces of the active fins and a part of the active fins' sidewalls substantially parallel to the major axis. Parallel gate lines are formed to cover the top surfaces and the exposed sidewalls of the active fins, cross over the active fins, and run on the isolation layer.

    摘要翻译： 提供了限定有源散热片的隔离方法，制造使用其的半导体器件的方法以及由此制造的半导体器件。 制造半导体器件的方法包括：制备半导体衬底; 并且在所述主轴和短轴的方向上形成具有主轴和短轴的多个有源散热片，并且二维排列在所述半导体基板上。 衬垫图案形成在活动鳍片的下侧壁上。 在具有衬垫图案的半导体衬底上形成隔离层，并且隔离层暴露活性鳍片的顶表面和基本上平行于长轴的活性鳍片侧壁的一部分。 形成平行栅极线以覆盖活性鳍片的顶表面和暴露的侧壁，跨过活性鳍片并且在隔离层上运行。