公开(公告)号：US20110006428A1

公开(公告)日：2011-01-13

申请号：US12617900

申请日：2009-11-13

申请人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L23/48

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

摘要翻译： 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

公开(公告)号：US20100123224A1

公开(公告)日：2010-05-20

申请号：US12271617

申请日：2008-11-14

申请人： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L23/58 ,  H01L21/312

CPC分类号： H01L21/3121 ,  C23C18/1212 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304

摘要： A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.

摘要翻译： 公开了一种提供改进的机械强度的半导体器件和制造方法。 半导体器件包括半导体衬底; 设置在半导体衬底上的粘附层; 以及设置在所述半导体衬底上的多孔低k膜，其中所述多孔低k膜包含致孔剂和包含至少一个Si-O-Si键合基团和至少一个桥连有机官能团的复合键合结构。

公开(公告)号：US20080277797A1

公开(公告)日：2008-11-13

申请号：US11747615

申请日：2007-05-11

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I. Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I. Bao

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

摘要翻译： 半导体结构包括在衬底上的第一电介质层。 至少一个第一导电结构在第一介电层内。 第一导电结构包括在第一介电层的顶表面上方延伸的盖部分。 至少一个第一电介质间隔物位于第一导电结构的帽部分的至少一个侧壁上。

公开(公告)号：US08736014B2

公开(公告)日：2014-05-27

申请号：US12271617

申请日：2008-11-14

申请人： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

发明人： Bo-Jiun Lin ,  Ching-Yu Lo ,  Hai-Ching Chen ,  Tien-I Bao ,  Chen-Hua Yu

IPC分类号： H01L21/31

CPC分类号： H01L21/3121 ,  C23C18/1212 ,  C23C18/122 ,  C23C18/1254 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02216 ,  H01L21/02282 ,  H01L21/02304

摘要： A semiconductor device and method for making such that provides improved mechanical strength is disclosed. The semiconductor device comprises a semiconductor substrate; an adhesion layer disposed over the semiconductor substrate; and a porous low-k film disposed over the semiconductor substrate, wherein the porous low-k film comprises a porogen and a composite bonding structure including at least one Si—O—Si bonding group and at least one bridging organic functional group.

摘要翻译： 公开了一种提供改进的机械强度的半导体器件和制造方法。 半导体器件包括半导体衬底; 设置在半导体衬底上的粘附层; 以及设置在所述半导体衬底上的多孔低k膜，其中所述多孔低k膜包含致孔剂和包含至少一个Si-O-Si键合基团和至少一个桥连有机官能团的复合键合结构。

公开(公告)号：US08710660B2

公开(公告)日：2014-04-29

申请号：US13554817

申请日：2012-07-20

申请人： Chen-Hua Yu ,  Tien-I Bao

发明人： Chen-Hua Yu ,  Tien-I Bao

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76885 ,  H01L23/53219 ,  H01L23/53223 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A device includes a first low-k dielectric layer, and a copper-containing via in the first low-k dielectric layer. The device further includes a second low-k dielectric layer over the first low-k dielectric layer, and an aluminum-containing metal line over and electrically coupled to the copper-containing via. The aluminum-containing metal line is in the second low-k dielectric layer.

公开(公告)号：US08264066B2

公开(公告)日：2012-09-11

申请号：US12617900

申请日：2009-11-13

申请人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

发明人： Ching-Yu Lo ,  Hung-Jung Tu ,  Hai-Ching Chen ,  Tien-I Bao ,  Wen-Chih Chiou ,  Chen-Hua Yu

IPC分类号： H01L29/40

CPC分类号： H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/02 ,  H01L2221/68372 ,  H01L2224/0557 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01019 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2224/05552 ,  H01L2924/00

摘要： An integrated circuit structure includes a semiconductor substrate; a through-semiconductor via (TSV) opening extending into the semiconductor substrate; and a TSV liner in the TSV opening. The TSV liner includes a sidewall portion on a sidewall of the TSV opening and a bottom portion at a bottom of the TSV opening. The bottom portion of the TSV liner has a bottom height greater than a middle thickness of the sidewall portion of the TSV liner.

摘要翻译： 集成电路结构包括半导体衬底; 贯穿半导体衬底的贯通半导体通孔（TSV）开口; 和TSV开口的TSV衬管。 TSV衬套包括在TSV开口的侧壁上的侧壁部分和TSV开口底部的底部。 TSV衬管的底部部分的底部高度大于TSV衬套的侧壁部分的中间厚度。

公开(公告)号：US20070202676A1

公开(公告)日：2007-08-30

申请号：US11361331

申请日：2006-02-24

申请人： Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

发明人： Ming Yeh ,  Chen-Hua Yu ,  Keng-Chu Lin ,  Tien-I Bao ,  Shwang-Ming Cheng

IPC分类号： H01L21/44

CPC分类号： H01L21/76834 ,  H01L21/02063 ,  H01L21/02126 ,  H01L21/02271 ,  H01L21/02304 ,  H01L21/02362 ,  H01L21/31633 ,  H01L21/31695 ,  H01L21/76808 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76846

摘要： A semiconductor structure having an opening formed in a porous dielectric layer is provided. The exposed pores of the dielectric layer along the sidewalls of the opening are sealed. The sealing may comprise a selective or a non-selective deposition method. The sealing layer has a substantially uniform thickness in one portion of the opening and a non-uniform thickness in another portion of the opening. A damascene interconnect structure having a pore sealing layer is provided as is its method of manufacture.

摘要翻译： 提供了一种形成在多孔电介质层中的开口的半导体结构。 沿着开口的侧壁的电介质层的暴露的孔被密封。 密封可以包括选择性或非选择性沉积方法。 密封层在开口的一部分中具有基本均匀的厚度，并且在开口的另一部分中具有不均匀的厚度。 如其制造方法那样提供具有孔密封层的镶嵌互连结构。

公开(公告)号：US06181013B2

公开(公告)日：2001-01-30

申请号：US09524521

申请日：2000-03-13

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L2348

CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基板的暴露表面和电介质层的暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料以通过蚀刻到电介质顶部水平来平坦化铜化合物，留下覆盖较窄孔中的铜导体的铜钝化化合物的薄层。

公开(公告)号：US06046108A

公开(公告)日：2000-04-04

申请号：US344402

申请日：1999-06-25

申请人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

发明人： Chung-Shi Liu ,  Chen-Hua Yu ,  Tien-I Bao ,  Syun-Ming Jang

IPC分类号： H01L21/768 ,  H01L21/44

CPC分类号： H01L21/76867 ,  H01L21/7684 ,  H01L21/76849

摘要： Form a dielectric layer on a surface of a conductive substrate with a trench through the top surface down to the substrate. Form a barrier layer over the dielectric layer including the exposed surface of the conductive substrate and the exposed sidewalls of the dielectric layer. Form a copper conductor over the barrier layer and overfilling the narrow hole in the trench. Etch away material from the surface of the copper conductor by a CMP process lowering the copper leaving a thin layer of copper over the barrier layer above the dielectric layer aside from the hole. Form a copper passivation by combining an element selected from silicon and germanium with copper on the exposed surfaces of the copper surfaces forming an interface in the narrower hole between the copper and the copper compound located below the dielectric top level. Etch away material from the surface of the copper compound and the barrier layer to planiarize the copper compound by etching down to the dielectric top level leaving a thin layer of the copper passivation compound covering the copper conductor in the narrower hole.

摘要翻译： 在具有沟槽的导电基底的表面上形成电介质层，通过顶表面向下延伸到衬底。 在包括导电基底的暴露表面和电介质层暴露的侧壁的电介质层上形成阻挡层。 在阻挡层上形成一个铜导体，并且填充沟槽中的窄孔。 通过CMP工艺从铜表面蚀刻掉材料，在除了孔之外的电介质层之上的阻挡层上方，降低铜，从而留下薄的铜层。 通过将选自硅和锗的元素与铜的暴露表面上的铜组合形成铜钝化，在铜和化合物之间的较窄的孔中形成界面，位于电介质顶层之下。 从铜化合物的表面和阻挡层的表面蚀刻掉材料，以通过蚀刻到电介质顶层来平面化铜化合物，留下在较窄的孔中覆盖铜导体的铜钝化化合物的薄层。

公开(公告)号：US08446012B2

公开(公告)日：2013-05-21

申请号：US11747615

申请日：2007-05-11

申请人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I. Bao

发明人： Chen-Hua Yu ,  Hai-Ching Chen ,  Tien-I. Bao

IPC分类号： H01L23/48

CPC分类号： H01L23/485 ,  H01L21/76826 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76898 ,  H01L23/5283 ,  H01L23/53223 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure includes a first dielectric layer over a substrate. At least one first conductive structure is within the first dielectric layer. The first conductive structure includes a cap portion extending above a top surface of the first dielectric layer. At least one first dielectric spacer is on at least one sidewall of the cap portion of the first conductive structure.

摘要翻译： 半导体结构包括在衬底上的第一电介质层。 至少一个第一导电结构在第一介电层内。 第一导电结构包括在第一介电层的顶表面上方延伸的盖部分。 至少一个第一电介质间隔物位于第一导电结构的帽部分的至少一个侧壁上。