公开(公告)号：US10777637B2

公开(公告)日：2020-09-15

申请号：US16256252

申请日：2019-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hong Yu ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/78

Abstract: One illustrative integrated circuit product disclosed herein includes a single diffusion break (SDB) isolation structure positioned between a first fin portion and a second fin portion, wherein the first fin portion comprises a first end surface and the second fin portion comprises a second end surface. In this example, the SDB structure includes a conformal liner layer that engages the first end surface of the first fin portion and the second end surface of the second fin portion, an insulating material positioned on the conformal liner layer, a cap structure positioned above an upper surface of the insulating material and an air gap positioned between a bottom surface of the cap structure and the upper surface of the insulating material.

公开(公告)号：US20200227404A1

公开(公告)日：2020-07-16

申请号：US16244169

申请日：2019-01-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Guowei Xu ,  Jiehui Shu ,  Ruilong Xie ,  Yurong Wen ,  Garo J. Derderian ,  Shesh M. Pandey ,  Laertis Economikos

IPC: H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L23/522

Abstract: An integrated circuit (IC) includes an active area including at least one active fin-type field effect transistor (FinFET), and a trench isolation adjacent to the active area. At least one inactive gate is positioned over the trench isolation. A vertically extending resistor body is positioned adjacent the at least one inactive gate over the trench isolation. A lower end of the resistor is below an upper surface of the trench isolation. The resistor reduces interconnect layer thickness to improve yield, and significantly reduces resistor footprint to enable scaling.

公开(公告)号：US10566195B2

公开(公告)日：2020-02-18

申请号：US15689668

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/768

Abstract: Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.

公开(公告)号：US20200002813A1

公开(公告)日：2020-01-02

申请号：US16023470

申请日：2018-06-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  John H. Zhang ,  Jinping Liu

IPC: C23C16/455

Abstract: Systems and methods for depositing a material by atomic layer deposition. A first gas distribution unit is configured to provide a first precursor to a first zone inside a reaction chamber. A second gas distribution unit is configured to provide a second precursor to a second zone inside the reaction chamber. A substrate support is arranged to hold the substrates inside the reaction chamber. The substrate support is configured to linearly move the substrates relative to the reaction chamber from the first zone to the second zone as part of a cyclic deposition cycle of an atomic layer deposition process depositing the film on each of the substrates held by the substrate support.

公开(公告)号：US20190355832A1

公开(公告)日：2019-11-21

申请号：US16523340

申请日：2019-07-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Chang Seo Park ,  Shimpei Yamaguchi ,  Tao Han ,  Yong Mo Yang ,  Jinping Liu ,  Hyuck Soo Yang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: One illustrative IC product disclosed herein includes first and second final gate structures and an insulating gate separation structure positioned between the first and second final gate structures. In one embodiment, the insulating gate separation structure has a stepped bottom surface with a substantially horizontally oriented bottom central surface that is surrounded by a substantially horizontally oriented recessed surface, wherein the substantially horizontally oriented bottom central surface is positioned a first level above the substrate and the substantially horizontally oriented recessed surface is positioned at a second level above the substrate, wherein the second level is greater than the first level.

公开(公告)号：US10475693B1

公开(公告)日：2019-11-12

申请号：US16002403

申请日：2018-06-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Hong Yu ,  Jinping Liu ,  Hui Zang

IPC: H01L21/76 ,  H01L21/762 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088

Abstract: A method includes forming a first hard mask layer above a substrate. The first hard mask layer is patterned to define a plurality of fin openings and at least a first diffusion break opening. A first etch process is performed to define a plurality of fins in the substrate and a first diffusion break recess in a selected fin. A first dielectric layer is formed between the fins and in the first diffusion break recess to define a first diffusion break. A second hard mask layer having a second opening positioned above the first diffusion break is formed above the first hard mask layer and the first dielectric layer. A second dielectric layer is formed in the second opening. The second hard mask layer is removed. A second etch process is performed to recess the first dielectric layer to expose upper portions of the plurality of fins.

公开(公告)号：US20190229019A1

公开(公告)日：2019-07-25

申请号：US15878081

申请日：2018-01-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Xusheng Wu ,  Haigou Huang ,  John H. Zhang ,  Pei Liu ,  Laertis Economikos

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/49 ,  H01L23/535 ,  H01L21/768

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a contact over an active gate structure and methods of manufacture. The structure includes: an active gate structure composed of conductive material located between sidewall material; an upper sidewall material above the sidewall material, the upper sidewall material being different material than the sidewall material; and a contact structure in electrical contact with the conductive material of the active gate structure. The contact structure is located between the sidewall material and between the upper sidewall material.

公开(公告)号：US10347541B1

公开(公告)日：2019-07-09

申请号：US15962808

申请日：2018-04-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  David Paul Brunco ,  Pei Liu ,  Shariq Siddiqui ,  Jinping Liu

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08

Abstract: A method of forming contacts over active gates is provided. Embodiments include forming first and second gate structures over a portion of a fin; forming a first and second RSD in a portion of the fin between the first gate structures and between the first and the second gate structure, respectively; forming TS structures over the first and second RSD; forming a first cap layer over the first and second gate structures or over the TS structures; forming a metal oxide liner over the substrate, trenches formed; filling the trenches with a second cap layer; forming an ILD layer over the substrate; forming a CA through a first portion of the ILD and metal oxide layer down to the TS structures over the second RSD; and forming a CB through a second portion of the ILD and metal oxide layer down to the first gate structures.

公开(公告)号：US10249496B2

公开(公告)日：2019-04-02

申请号：US15587597

申请日：2017-05-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xusheng Yu ,  John H. Zhang ,  Xiaoqiang Zhang

IPC: H01L21/033 ,  H01L23/525 ,  H01L23/532 ,  H01L21/311

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first mandrel line, a second mandrel line, and a non-mandrel line between the first mandrel line and the second mandrel line are provided. A first sidewall spacer is formed adjacent to a section of the first mandrel line and is arranged between the section of the first mandrel line and the non-mandrel line. A first cut is formed that extends partially across the non-mandrel line adjacent to the first spacer to narrow a section of the non-mandrel line. The section of the first mandrel line is removed selective to the first sidewall spacer to form a second cut. An interconnect is formed using the non-mandrel line. The interconnect includes a narrowed section coinciding with a location of the narrowed section of the non-mandrel line.

公开(公告)号：US20190067010A1

公开(公告)日：2019-02-28

申请号：US15689668

申请日：2017-08-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Jinping Liu ,  Rui Chen

IPC: H01L21/033 ,  H01L21/311 ,  H01L21/3105

CPC classification number: H01L21/0338 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31051 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76816

Abstract: Methods of multiple patterning. First and second mandrel lines are formed on a patternable layer. Sidewall spacers are formed on the patternable layer adjacent to the first mandrel line and adjacent to the second mandrel line. A portion of the first mandrel line is removed to form a gap in the first mandrel line. A gapfill material is deposited in the gap in the first mandrel line. The gapfill material and sidewall spacers are composed of the same material.