公开(公告)号：US10937685B2

公开(公告)日：2021-03-02

申请号：US16446588

申请日：2019-06-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Haiting Wang ,  Jiehui Shu

IPC: H01L21/768 ,  H01L21/762 ,  H01L21/8234 ,  H01L27/092 ,  H01L27/088

Abstract: The present disclosure generally relates to semiconductor devices and processing. The present disclosure also relates to isolation structures formed in active regions, more particularly, diffusion break structures in an active semiconductor layer of a semiconductor device. The present disclosure also relates to methods of forming such structures and replacement metal gate processes.

公开(公告)号：US20210050419A1

公开(公告)日：2021-02-18

申请号：US16541600

申请日：2019-08-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Baofu Zhu ,  Haiting Wang ,  Sipeng Gu

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/092

Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A gate structure is arranged over a channel region of a semiconductor body. A first source/drain region is coupled to a first portion of the semiconductor body, and a second source/drain region is located in a second portion the semiconductor body. The first source/drain region includes an epitaxial semiconductor layer containing a first concentration of a dopant. The second source/drain region contains a second concentration of the dopant. The channel region is positioned in the semiconductor body between the first source/drain region and the second source/drain region.

公开(公告)号：US20210050412A1

公开(公告)日：2021-02-18

申请号：US16538785

申请日：2019-08-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Chun Yu WONG ,  Haiting Wang ,  Yong Jun Shi ,  Xiaoming Yang ,  Liu Jiang

IPC: H01L29/06 ,  H01L23/66 ,  H01L21/764 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes an active region, a first structure, a second gate structure, a first gate dielectric sidewall, a second gate dielectric sidewall, a first air gap region, a second air gap region and a contact structure. The active region is formed over a substrate. The first and second gate structures are formed over the active region and between the first gate structure and the second gate structure are the first gate dielectric sidewall, the first air gap region, the contact structure, the second air gap region and a second gate dielectric sidewall.

公开(公告)号：US20200350202A1

公开(公告)日：2020-11-05

申请号：US16400481

申请日：2019-05-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiaoming Yang ,  Haiting Wang ,  Hong Yu ,  Jeffrey Chee ,  Guoliang Zhu

IPC: H01L21/768 ,  H01L23/528 ,  H01L23/522 ,  H01L21/033

Abstract: Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.

公开(公告)号：US10818498B1

公开(公告)日：2020-10-27

申请号：US16407744

申请日：2019-05-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Haiting Wang ,  Hui Zang

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78 ,  H01L29/40 ,  H01L21/02 ,  H01L29/417 ,  H01L21/768

Abstract: Structures for a field effect-transistor and methods of forming a structure for a field-effect transistor. A gate electrode arranged adjacent to an outer sidewall spacer and an inner sidewall spacer. The gate electrode has a top surface that is recessed relative to the outer sidewall spacer and the inner sidewall spacer. A gate cap includes a first section of a first width arranged over the first section of the gate electrode and a second section of a second width arranged over the first section of the gate cap and the inner sidewall spacer. The second width is greater than the first width, and the inner sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US20200168731A1

公开(公告)日：2020-05-28

申请号：US16776807

申请日：2020-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Chung Foong Tan ,  Guowei Xu ,  Haiting Wang ,  Yue Zhong ,  Ruilong Xie ,  Tek Po Rinus Lee ,  Scott Beasor

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/306 ,  H01L21/768 ,  H01L29/08

Abstract: An integrated circuit product is disclosed that includes a transistor device that includes a final gate structure, a gate cap, a low-k sidewall spacer positioned on and in contact with opposing sidewalls of the final gate structure, first and second contact etch stop layers (CESLs) located on opposite sides of the final gate structure, whereby the CESLs are positioned on and in contact with the low-k sidewall spacer, and a high-k spacer located on opposite sides of the final gate structure, wherein the high-k spacer is positioned in recesses formed in an upper portion of the CESLs.

公开(公告)号：US20200066899A1

公开(公告)日：2020-02-27

申请号：US16664056

申请日：2019-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/78 ,  H01L21/02 ,  H01L29/423 ,  H01L29/66 ,  H01L29/49

Abstract: A transistor device disclosed herein includes, among other things, a gate electrode positioned above a semiconductor material region, a sidewall spacer positioned adjacent the gate electrode, a gate insulation layer having a first portion positioned between the gate electrode and the semiconductor material region and a second portion positioned between a lower portion of the sidewall spacer and the gate electrode along a portion of a sidewall of the gate electrode, an air gap cavity located between the sidewall spacer and the gate electrode and above the second portion of the gate insulation layer, and a gate cap layer positioned above the gate electrode, wherein the gate cap layer seals an upper end of the air gap cavity so as to define an air gap positioned adjacent the gate electrode.

公开(公告)号：US10535771B1

公开(公告)日：2020-01-14

申请号：US16016828

申请日：2018-06-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Laertis Economikos ,  Shesh Mani Pandey ,  Hui Zang ,  Haiting Wang ,  Jinping Liu

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02

Abstract: A method of forming transistor devices with an air gap in the replacement gate structure is disclosed including forming a placeholder gate structure above a semiconductor material region, forming a sidewall spacer adjacent the placeholder gate structure, removing the placeholder gate structure to define a gate cavity bounded by the sidewall spacer, forming a gate insulation layer in the gate cavity, the gate insulation layer including a first portion having a first thickness and a second portion having a second thickness greater than the first thickness, forming a gate electrode in the gate cavity above the gate insulation layer, removing at least a portion of the second portion of the gate insulation layer to define an air gap cavity adjacent the gate electrode, and forming a first gate cap layer above the gate electrode, wherein the first gate cap layer seals an upper end of the air gap cavity.

公开(公告)号：US20200013678A1

公开(公告)日：2020-01-09

申请号：US16026130

申请日：2018-07-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sipeng Gu ,  Akshey Sehgal ,  Xinyuan Dou ,  Sunil K. Singh ,  Ravi P. Srivastava ,  Haiting Wang ,  Scott H. Beasor

IPC: H01L21/8234 ,  H01L29/08 ,  H01L29/423 ,  H01L23/48 ,  H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L29/66

Abstract: This disclosure is directed to an integrated circuit (IC) structure. The IC structure may include a semiconductor structure including two source/drain regions; a metal gate positioned on the semiconductor structure adjacent to and between the source/drain regions; a metal cap with a different metal composition than the metal gate and having a thickness in the range of approximately 0.5 nanometer (nm) to approximately 5 nm positioned on the metal gate; a first dielectric cap layer positioned above the semiconductor structure; an inter-layer dielectric (ILD) positioned above the semiconductor structure and laterally abutting both the metal cap and the metal gate, wherein an upper surface of the ILD has a greater height above the semiconductor structure than an upper surface of the metal gate; a second dielectric cap layer positioned on the ILD and above the metal cap; and a contact on and in electrical contact with the metal cap.

公开(公告)号：US10522538B1

公开(公告)日：2019-12-31

申请号：US16032108

申请日：2018-07-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Haiting Wang ,  Shesh Mani Pandey ,  Jiehui Shu ,  Laertis Economikos ,  Hui Zang ,  Ruilong Xie ,  Guowei Xu ,  Zhaoying Hu

IPC: H01L29/08 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/40

Abstract: Parallel fins are formed (in a first orientation), and source/drain structures are formed in or on the fins, where channel regions of the fins are between the source/drain structures. Parallel gate structures are formed to intersect the fins (in a second orientation perpendicular to the first orientation), source/drain contacts are formed on source/drain structures that are on opposite sides of the gate structures, and caps are formed on the source/drain contacts. After forming the caps, a gate cut structure is formed interrupting the portion of the gate structure that extends between adjacent fins. The upper portion of the gate cut structure includes extensions, where a first extension extends into one of the caps on a first side of the gate cut structure, and a second extension extends into the inter-gate insulator on a second side of the gate cut structure.