公开(公告)号：US10714616B2

公开(公告)日：2020-07-14

申请号：US15678206

申请日：2017-08-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Andres Bryant ,  Edward J. Nowak

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L21/3115 ,  H01L21/762

Abstract: A semiconductor device including semiconductor material having a bend and a trench feature formed at the bend, and a gate structure at least partially disposed in the trench feature. A method of fabricating a semiconductor structure including forming a semiconductor material with a trench feature over a layer, forming a gate structure at least partially in the trench feature, and bending the semiconductor material such that stress is induced in the semiconductor material in an inversion channel region of the gate structure.

公开(公告)号：US20180175025A1

公开(公告)日：2018-06-21

申请号：US15893860

申请日：2018-02-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823468 ,  H01L21/823487 ,  H01L29/1037 ,  H01L29/66666 ,  H01L29/7827

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

公开(公告)号：US09911738B1

公开(公告)日：2018-03-06

申请号：US15586621

申请日：2017-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hiroaki Niimi ,  Kwan-Yong Lim ,  Brent A. Anderson ,  Junli Wang

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L21/8238

CPC classification number: H01L27/092 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823885 ,  H01L29/42376 ,  H01L29/7827

Abstract: Methods for forming a structure that includes vertical-transport field-effect transistors and structures that include vertical-transport field-effect transistors. A first semiconductor fin is separated from a second semiconductor fin by a gap. A gate stack is conformally deposited that extends across the first semiconductor fin, the second semiconductor fin, and the gap. A section of the gate stack is located in the gap. A gate strap layer is formed in the gap on the section of the gate stack. The gate stack is patterned to form a first gate electrode associated with the first semiconductor fin and a second gate electrode associated with the second semiconductor fin. The gate strap layer masks the section of the gate stack when the gate stack is patterned. The first gate electrode is connected with the second gate electrode by the gate strap layer and the section of the gate stack.

公开(公告)号：US20170236917A1

公开(公告)日：2017-08-17

申请号：US15044431

申请日：2016-02-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Brent A. Anderson ,  Andreas Scholze

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L29/66795 ,  H01L29/785

Abstract: One aspect of the disclosure provides for a method of forming a replacement gate structure. The method may include: removing a dummy gate from over a set of fins to form an opening in a dielectric layer exposing the set of fins, each fin in the set of fins being substantially separated from an adjacent fin in the set of fins via an dielectric; forming a protective cap layer within the opening over the exposed set of fins; removing a portion of the dielectric on each side of each fin in the set of fins; undercutting each fin by removing a portion of each fin in the set of fins to create a notch disposed under the protective cap layer; substantially filling each notch with an oxide; forming a gate dielectric over each fin in the set of fins; and forming a gate conductor over the gate dielectric, thereby forming the replacement gate structure.

公开(公告)号：US20170186682A1

公开(公告)日：2017-06-29

申请号：US14980320

申请日：2015-12-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/3105 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/76835 ,  H01L21/31051 ,  H01L21/31053 ,  H01L21/31144 ,  H01L21/7681 ,  H01L21/76819 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53295

Abstract: A method of forming a via and a wiring structure formed are disclosed. The method may include forming a conductive line in a first dielectric layer; forming a hard mask adjacent to the conductive line after the conductive line forming; forming a second dielectric layer over the hard mask; and forming a via opening to the conductive line in the second dielectric layer. The via opening lands at least partially on the hard mask to self-align the via opening to the conductive line. A via may be formed by filling the via opening with a conductor.

公开(公告)号：US09552852B2

公开(公告)日：2017-01-24

申请号：US14534205

申请日：2014-11-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Kota V. R. M. Murali ,  Edward J. Nowak

IPC: H01L45/00 ,  H01L27/105 ,  G11C7/10 ,  H01L21/768 ,  H03K5/13 ,  H01L27/24 ,  G11C7/02

CPC classification number: G11C7/106 ,  G11C7/02 ,  H01L21/76895 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/1206 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/16 ,  H03K5/13

Abstract: Some embodiments of the present invention may include one, or more, of the following features, characteristics or advantages: (i) latch device including multiple Ecrit material regions all electrically connected to a common terminal (sometimes structured and shaped in the form of a storage plate conductor); (ii) bi-stable three-terminal latch device using two Ecrit property regions; (iii) three-terminal, two-Ecrit-region latch device where, for each Ecrit region, (Vdd−Vss) divided by (region thickness, dn) is greater than the region's Ecrit value; or (iv) use of multiple Ecrit material region latch devices to provide data storage instrumentality in a static memory device.

Abstract translation: 本发明的一些实施例可以包括以下特征，特征或优点中的一个或多个：（i）闩锁装置，包括多个Ecrit材料区域，所述Ecrit材料区域全部电连接到公共端子（有时结构化并以存储器的形式形成 板导体）; （ii）使用两个Ecrit属性区域的双稳态三端锁存装置; （iii）三端，双E区域锁存装置，其中对于每个Ecrit区域（Vdd-Vss）除以（区域厚度dn）大于该区域的Ecrit值; 或（iv）使用多个Ecrit材料区域锁存器件来在静态存储器件中提供数据存储器具。

公开(公告)号：US09520391B1

公开(公告)日：2016-12-13

申请号：US14996371

申请日：2016-01-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Terence B. Hook ,  Myung-Hee Na ,  Edward J. Nowak

IPC: H01L27/06 ,  H01L29/786 ,  H01L21/8238

CPC classification number: H01L27/0629 ,  H01L21/823857 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/78648

Abstract: Methods form complementary metal oxide semiconductor (CMOS) devices that include a first transistor and a complementary second transistor, and an output connected to the first transistor and the second transistor. The first transistor includes a first channel region, a first back gate, a first delay element between the output and the first back gate, and a first back gate insulator separating the first back gate from the first channel region. The second transistor includes a second channel region, a second back gate, a second delay element between the output and the second back gate, and a second back gate insulator separating the second back gate from the second channel region. The first delay element, the first back gate insulator, and the first channel region form a first resistor-capacitor (RC) circuit, and the second delay element, the second back gate insulator, and the second channel region form a second RC circuit.

Abstract translation: 方法形成包括第一晶体管和互补第二晶体管的互补金属氧化物半导体（CMOS）器件，以及连接到第一晶体管和第二晶体管的输出。 第一晶体管包括第一沟道区，第一后栅，在输出和第一后栅之间的第一延迟元件，以及将第一后栅与第一沟道区分开的第一后栅绝缘体。 第二晶体管包括第二沟道区，第二后栅，输出与第二后栅之间的第二延迟元件，以及将第二栅极与第二沟道区分开的第二栅极绝缘体。 第一延迟元件，第一背栅绝缘体和第一沟道区形成第一电阻 - 电容（RC）电路，第二延迟元件，第二后栅极绝缘体和第二沟道区形成第二RC电路。

公开(公告)号：US10269707B2

公开(公告)日：2019-04-23

申请号：US15634135

申请日：2017-06-27

Applicant: GlobalFoundries Inc.

Inventor： Brent A. Anderson ,  Jeffrey B. Johnson ,  Edward J. Nowak

IPC: H01L21/28 ,  H01L29/66 ,  H01L21/768 ,  H01L23/485 ,  H01L23/535 ,  H01L29/78 ,  H01L23/528

Abstract: Disclosed are semiconductor structures comprising a field effect transistor (FET) having a low-resistance source/drain contact and, optionally, low gate-to-source/drain contact capacitance. The structures comprise a semiconductor body and, contained therein, first and second source/drain regions and a channel region. A first gate is adjacent to the semiconductor body at the channel region and a second, non-functioning, gate is adjacent to the semiconductor body such that the second source/drain region is between the first and second gates. First and second source/drain contacts are on the first and source/drain regions, respectively. The second source/drain contact is wider than the first and, thus, has a lower resistance. Additionally, spacing of the first and second source/drain contacts relative to the first gate can be such that the first gate-to-second source/drain contact capacitance is equal to or less than the first gate-to-first source/drain contact capacitance. Also disclosed are associated formation methods.

公开(公告)号：US09929152B2

公开(公告)日：2018-03-27

申请号：US15198309

申请日：2016-06-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Brent A. Anderson ,  Edward J. Nowak

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823468 ,  H01L21/823487

Abstract: One aspect of the disclosure relates to an integrated circuit structure. The integrated circuit structure may include a fin having a first source/drain region and a second source/drain, the first source/drain region being over a substrate and below a central region of the fin, and the second source/drain region being within a dielectric layer and over the central region of the fin; a gate structure within the dielectric layer substantially surrounding the central region of the fin between the first source/drain region and the second source drain region, wherein the fin includes at least one tapered region from the central region of the fin to at least one of the first source/drain region or the second source/drain region.

公开(公告)号：US09847416B1

公开(公告)日：2017-12-19

申请号：US15351597

申请日：2016-11-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Robert R. Robison ,  Brent A. Anderson

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423 ,  H01L29/04 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7843 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66666 ,  H01L29/78642 ,  H01L29/78696

Abstract: Disclosed are performance-enhanced vertical devices (e.g., vertical field effect transistors (FETs) or complementary metal oxide semiconductor (CMOS) devices, which incorporate vertical FETs) and methods of forming such devices. A strained dielectric layer is positioned laterally adjacent to the gate of a vertical FET, increasing the charge carrier mobility within the channel region and improving performance. In a vertical n-type FET (NFET), the strain is compressive to improve electron mobility given the direction of current within the vertical NFET; whereas, in a vertical p-type FET (PFET), the strain is tensile to improve hole mobility given the direction of current within the vertical PFET. Optionally, the orientation of a vertical FET relative to the surface plane of the semiconductor wafer on which it is formed is also preplanned as function of the type of FET (i.e., NFET or PFET) for optimal charge carrier mobility and, thereby enhanced performance.