公开(公告)号：US20180254343A1

公开(公告)日：2018-09-06

申请号：US15971419

申请日：2018-05-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Christian Schippel ,  Alban Zaka ,  Ignasi Cortes Mayol

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/762 ,  H01L21/265 ,  H01L29/45 ,  H01L29/167 ,  H01L29/08 ,  H01L29/10 ,  H01L29/06

CPC classification number: H01L29/7824 ,  H01L21/26513 ,  H01L21/76224 ,  H01L21/76229 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1079 ,  H01L29/167 ,  H01L29/45 ,  H01L29/66628 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7835

Abstract: A method of forming a semiconductor device includes forming a first well and a second well in a substrate, wherein the first well is doped with dopants of a first conductivity type and the second well is doped with dopants of a second conductivity type. A third well is formed within the first well, and a gate structure is formed above the substrate, the gate structure partially overlying at least the first and second wells. A first epi region is formed on the third well, wherein the first epi region is doped with second dopants of the second conductivity type, and a drain region is formed that is electrically coupled to the second well.

公开(公告)号：US09711513B2

公开(公告)日：2017-07-18

申请号：US14918048

申请日：2015-10-20

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Sven Beyer ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L27/12 ,  H01L27/11524 ,  H01L27/11529 ,  H01L21/28

CPC classification number: H01L27/11524 ,  H01L21/28273 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11539 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A semiconductor structure includes a nonvolatile memory cell including a source region, a channel region and a drain region that are provided in a semiconductor material. The channel region includes a first portion adjacent the source region and a second portion between the first portion of the channel region and the drain region. An electrically insulating floating gate is provided over the first portion of the channel region. The nonvolatile memory cell further includes a select gate and a control gate. The first portion of the select gate is provided over the second portion of the channel region. The second portion of the select gate is provided over a portion of the floating gate that is adjacent to the first portion of the select gate. The control gate is provided over the floating gate and adjacent to the second portion of the select gate.

公开(公告)号：US09460955B2

公开(公告)日：2016-10-04

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/02 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US09312189B2

公开(公告)日：2016-04-12

申请号：US14244651

申请日：2014-04-03

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Alban Zaka ,  Ran Yan ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/425 ,  H01L21/8238 ,  H01L21/265 ,  H01L21/266 ,  H01L21/324 ,  H01L29/66 ,  H01L29/167 ,  H01L27/092

CPC classification number: H01L21/823814 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/268 ,  H01L21/324 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823807 ,  H01L27/0924 ,  H01L29/1041 ,  H01L29/167 ,  H01L29/66492 ,  H01L29/6656 ,  H01L29/6659

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a structure having an n-channel gate stack and a p-channel gate stack formed over a semiconductor substrate. The method includes forming halo implant regions in the semiconductor substrate adjacent the p-channel gate stack and forming extension implant regions in the semiconductor substrate adjacent the p-channel gate stack. The method further includes annealing the halo implant regions and the extension implant regions in the semiconductor substrate adjacent the p-channel gate stack by performing a laser anneal process. Also, the method forms extension implant regions in the semiconductor substrate adjacent the n-channel gate stack.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供在半导体衬底上形成的具有n沟道栅极叠层和p沟道栅叠层的结构。 该方法包括在邻近p沟道栅极叠层的半导体衬底中形成卤素注入区，并在邻近p沟道栅叠层的半导体衬底中形成延伸注入区。 该方法还包括通过执行激光退火工艺来退火邻近p沟道栅叠层的半导体衬底中的卤注入区和延伸注入区。 此外，该方法在邻近n沟道栅叠层的半导体衬底中形成延伸注入区。

公开(公告)号：US20150145000A1

公开(公告)日：2015-05-28

申请号：US14092232

申请日：2013-11-27

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ran Yan ,  Nicolas Sassiat ,  Alban Zaka ,  Kun-Hsien Lin

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L21/76224 ,  H01L29/0653 ,  H01L29/66636 ,  H01L29/7848

Abstract: Integrated circuits with electrical components near shallow trench isolations and methods for producing such integrated circuits are provided. The method includes forming a trench is a substrate, where the trench has a trench surface. A barrier layer including silicon and germanium is formed overlying the trench surface. A shallow trench isolation is then formed with a core overlying the barrier layer, where the core includes a shallow trench isolation insulator.

Abstract translation: 提供了具有靠近浅沟槽隔离的电气部件的集成电路以及用于制造这种集成电路的方法。 该方法包括形成沟槽是衬底，其中沟槽具有沟槽表面。 包括硅和锗的阻挡层形成在沟槽表面上。 然后用覆盖阻挡层的芯形成浅沟槽隔离，其中芯包括浅沟槽隔离绝缘体。

公开(公告)号：US20140361385A1

公开(公告)日：2014-12-11

申请号：US13911857

申请日：2013-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ran Yan ,  Nicolas Sassiat ,  El Mehdi Bazizi ,  Jan Hoentschel

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L21/265 ,  H01L21/2658 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/51 ,  H01L29/6659 ,  H01L29/7833

Abstract: Methods of forming a semiconductor device structure at advanced technology nodes and respective semiconductor device structures are provided at advanced technology nodes, i.e., smaller than 100 nm. In some illustrative embodiments, a fluorine implantation process for implanting fluorine at least into a polysilicon layer formed over a dielectric layer structure is performed prior to patterning the gate dielectric layer structure and the polysilicon layer for forming a gate structure and implanting source and drain regions at opposing sides of the gate structure.

Abstract translation: 在先进技术节点上形成半导体器件结构的方法和相应的半导体器件结构在低于100nm的技术节点上提供。 在一些说明性实施例中，在将栅极电介质层结构和用于形成栅极结构的多晶硅层图案化并且将源极和漏极区域注入到其中之前，至少将至少注入形成在电介质层结构上的多晶硅层中的氟注入工艺 门结构的两侧。

公开(公告)号：US10580863B2

公开(公告)日：2020-03-03

申请号：US15728679

申请日：2017-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Damien Angot ,  Alban Zaka ,  Tom Herrmann ,  Venkata Naga Ranjith Kuma Nelluri ,  Jan Hoentschel ,  Lars Mueller-Meskamp ,  Martin Gerhardt

IPC: H01L27/088 ,  H01L21/336 ,  H01L27/12 ,  H01L31/0392 ,  H01L29/10 ,  H01L21/84 ,  H01L29/66 ,  H01L21/225 ,  H01L29/786 ,  H01L29/06 ,  H01L29/417 ,  H01L29/78

Abstract: In sophisticated semiconductor devices, the lateral electric field in fully depleted transistor elements operated at elevated supply voltages may be significantly reduced by establishing a laterally graded dopant profile at edge regions of the respective channel regions. In some illustrative embodiments to this end, one or more dopant species may be incorporated prior to completing the gate electrode structure.

公开(公告)号：US20190157451A1

公开(公告)日：2019-05-23

申请号：US15819825

申请日：2017-11-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ignasi Cortes Mayol ,  Alban Zaka ,  Tom Herrmann ,  El Mehdi Bazizi

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/08 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an LDMOS device on FDSOI structures and methods of manufacture. The laterally double diffused semiconductor device includes a gate dielectric composed of a buried insulator material of a semiconductor on insulator (SOI) technology, a channel region composed of semiconductor material of the SOI technology and source/drain regions on a front side of the buried insulator material such that a gate is formed on a back side of the buried insulator material. The gate terminal can also be placed at a hybrid section used as a back-gate voltage to control the channel and the drift region of the device.

公开(公告)号：US20180090558A1

公开(公告)日：2018-03-29

申请号：US15277583

申请日：2016-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Alban Zaka ,  Ignasi Cortes Mayol ,  Tom Herrmann ,  Andrei Sidelnicov ,  El Mehdi Bazizi

IPC: H01L49/02 ,  H01L23/535 ,  H01L29/36

CPC classification number: H01L28/60 ,  H01L23/535 ,  H01L29/94

Abstract: A capacitor, such as an N-well capacitor, in a semiconductor device includes a floating semiconductor region, which allows a negative biasing of the channel region of the capacitor while suppressing leakage into the depth of the substrate. In this manner, N-well-based capacitors may be provided in the device level and may have a substantially flat capacitance/voltage characteristic over a moderately wide range of voltages. Consequently, alternating polarity capacitors formed in the metallization system may be replaced by semiconductor-based N-well capacitors.

公开(公告)号：US09905707B1

公开(公告)日：2018-02-27

申请号：US15337026

申请日：2016-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andrei Sidelnicov ,  Alban Zaka ,  El Mehdi Bazizi ,  Venkata Naga Ranjith Kumar Nelluri ,  Juergen Faul

IPC: H01L29/00 ,  H01L29/94 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L29/94 ,  H01L21/265 ,  H01L29/66174

Abstract: Capacitive structures in the device level of sophisticated MOS devices may be formed so as to exhibit a significantly reduced capacitance/voltage variability. To this end, a highly doped semiconductor region may be formed in the “channel” of the capacitive structure. For example, for a specified concentration of the dopant species and a specified range of the vertical dimension of the highly doped semiconductor region, a reduced variability of approximately 3% or less may be obtained for a voltage range of, for example, ±5 V.