公开(公告)号：US20180366484A1

公开(公告)日：2018-12-20

申请号：US15622497

申请日：2017-06-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Jochen Willi. Poth ,  Sven Beyer ,  Stefan Duenkel ,  Sandhya Chandrashekhar ,  Zhi-Yuan Wu

IPC: H01L27/11568 ,  H01L29/06 ,  H01L29/423 ,  H01L29/792 ,  H01L29/66

CPC classification number: H01L27/11568 ,  H01L21/84 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/78648 ,  H01L29/792

Abstract: In sophisticated SOI transistor elements, the buried insulating layer may be specifically engineered so as to include non-standard dielectric materials. For instance, a charge-trapping material and/or a high-k dielectric material and/or a ferroelectric material may be incorporated into the buried insulating layer. In this manner, non-volatile storage transistor elements with superior performance may be obtained and/or efficiency of a back-bias mechanism may be improved.

公开(公告)号：US09941348B2

公开(公告)日：2018-04-10

申请号：US15142332

申请日：2016-04-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ran Yan ,  Ming-Cheng Chang ,  Ralf Richter

IPC: H01L21/02 ,  H01L49/02 ,  H01L21/762

CPC classification number: H01L28/84 ,  H01L21/76283 ,  H01L28/40 ,  H01L28/82

Abstract: The present disclosure provides a method of forming a capacitor structure and a capacitor structure. A semiconductor-on-insulator substrate is provided comprising a semiconductor layer, a buried insulating material layer and a semiconductor substrate material. A shallow trench isolation structure defining a first active region on the SOI substrate is formed, the first active region having a plurality of trenches formed therein. Within each trench, the semiconductor substrate material is exposed on inner sidewalls and a bottom face. A layer of insulating material covering the exposed semiconductor substrate material is formed, and an electrode material is deposited on the layer of insulating material in the first active region.

公开(公告)号：US20160268426A1

公开(公告)日：2016-09-15

申请号：US15161399

申请日：2016-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L29/7843 ,  H01L21/823412 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes a plurality of spaced apart fins, a dielectric material layer positioned between each of the plurality of spaced apart fins, and a common gate structure positioned above the dielectric material layer and extending across the fins. A continuous merged semiconductor material region is positioned on each of the fins and above the dielectric material layer, is laterally spaced apart from the common gate structure, extends between and physically contacts the fins, has a first sidewall surface that faces toward the common gate structure, and has a second sidewall surface that is opposite of the first sidewall surface and faces away from the common gate structure. A stress-inducing material is positioned in a space defined by at least the first sidewall surface, opposing sidewall surfaces of an adjacent pair of fins, and an upper surface of the dielectric material layer.

Abstract translation: 半导体器件包括多个间隔开的翅片，位于多个间隔开的翅片中的每一个之间的介电材料层，以及位于电介质材料层上方并延伸穿过翅片的公共栅极结构。 连续合并的半导体材料区域位于每个散热片上并且位于电介质材料层上方，与公共栅极结构横向间隔开，在翅片之间延伸并物理接触翅片，具有面向公共栅极结构的第一侧壁表面 并且具有与第一侧壁表面相对并且远离公共栅极结构的第二侧壁表面。 应力诱导材料定位在由至少第一侧壁表面，相邻的一对翅片的相对侧壁表面和介电材料层的上表面限定的空间中。

公开(公告)号：US09412848B1

公开(公告)日：2016-08-09

申请号：US14615529

申请日：2015-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Javorka ,  Jan Hoentschel ,  Stefan Flachowsky

IPC: H01L21/331 ,  H01L21/8222 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/42392 ,  H01L29/66772 ,  H01L29/78696

Abstract: The present disclosure provides a method of forming a semiconductor device and a semiconductor device. An SOI substrate portion having a semiconductor layer, a buried insulating material layer and a bulk substrate is provided, wherein the buried insulating material layer is interposed between the semiconductor layer and the bulk substrate. The SOI substrate portion is subsequently patterned so as to form a patterned bi-layer stack on the bulk substrate, which bi-layer stack comprises a patterned semiconductor layer and a patterned buried insulating material layer. The bi-layer stack is further enclosed with a further insulating material layer and an electrode material is formed on and around the further insulating material layer. Herein a gate electrode is formed by the bulk substrate and the electrode material such that the gate electrode substantially surrounds a channel portion formed by a portion of the patterned buried insulating material layer.

Abstract translation: 本公开提供了形成半导体器件和半导体器件的方法。 提供具有半导体层，掩埋绝缘材料层和体基板的SOI衬底部分，其中埋入绝缘材料层插入在半导体层和块状衬底之间。 SOI衬底部分随后被图案化以便在本体衬底上形成图案化的双层堆叠，该双层堆叠包括图案化的半导体层和图案化的掩埋绝缘材料层。 双层堆叠进一步被另外的绝缘材料层封闭，并且在另外的绝缘材料层上和周围形成电极材料。 这里，栅电极由体基板和电极材料形成，使得栅电极基本上围绕由图案化的掩埋绝缘材料层的一部分形成的沟道部分。

公开(公告)号：US09391176B2

公开(公告)日：2016-07-12

申请号：US14522000

申请日：2014-10-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L25/00 ,  H01L29/06 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/165 ,  H01L25/065 ,  H01L29/786 ,  H01L29/423

CPC classification number: H01L29/66818 ,  H01L25/0657 ,  H01L29/0634 ,  H01L29/0673 ,  H01L29/165 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/785 ,  H01L29/78645 ,  H01L29/78648 ,  H01L29/78687 ,  H01L29/78696 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure provides, in various aspects of the present disclosure, a semiconductor device which includes a semiconductor stack disposed over a surface of a substrate and a gate structure partially formed over an upper surface and two opposing sidewall surfaces of the semiconductor stack, wherein the semiconductor stack includes an alternating arrangement of at least two layers formed by a first semiconductor material and a second semiconductor material which is different from the first semiconductor material.

Abstract translation: 本公开在本公开的各个方面提供一种半导体器件，其包括设置在衬底的表面上的半导体堆叠和部分地形成在半导体堆叠的上表面和两个相对的侧壁表面上的栅极结构，其中， 半导体堆叠包括由第一半导体材料和与第一半导体材料不同的第二半导体材料形成的至少两层的交替布置。

公开(公告)号：US09054044B2

公开(公告)日：2015-06-09

申请号：US13788719

申请日：2013-03-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stefan Flachowsky ,  Jan Hoentschel ,  Ralf Richter ,  Peter Javorka

IPC: H01L29/06 ,  H01L21/308 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L21/3083 ,  H01L29/0657 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7853 ,  H01L29/7854

Abstract: Semiconductor device structures and methods for forming a semiconductor device are provided. In embodiments, one or more fins are provided, each of the one or more fins having a lower portion and an upper portion disposed on the lower portion. The lower portion is embedded in a first insulating material. The shape of the upper portion is at least one of a substantially triangular shape and a substantially rounded shape and a substantially trapezoidal shape. Furthermore, a layer of a second insulating material different from the first insulating material is formed on the upper portion.

Abstract translation: 提供了用于形成半导体器件的半导体器件结构和方法。 在实施例中，提供一个或多个翅片，所述一个或多个翅片中的每一个具有设置在下部的下部和上部。 下部嵌入第一绝缘材料中。 上部的形状是基本上三角形形状和大致圆形形状和大致梯形形状中的至少一个。 此外，在上部形成有与第一绝缘材料不同的第二绝缘材料层。

公开(公告)号：US20140273375A1

公开(公告)日：2014-09-18

申请号：US13842077

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Peter Javorka ,  Ralf Richter ,  Jan Hoentschel

IPC: H01L21/266 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L21/823418 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/823412 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/6656

Abstract: Methods for fabricating an integrated circuit are provided herein. In an embodiment, a method for fabricating an integrated circuit includes forming a gate electrode structure overlying a semiconductor substrate. A first sacrificial oxide layer is formed overlying the semiconductor substrate and a first implant mask is patterned overlying the first sacrificial oxide layer to expose a portion of the first sacrificial oxide layer adjacent the gate electrode structure. Conductivity determining ions are implanted into the semiconductor substrate, through the first sacrificial oxide layer. The first implant mask and the first sacrificial oxide layer are removed after implanting the conductivity determining ions into the semiconductor substrate.

Abstract translation: 本文提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括形成覆盖半导体衬底的栅电极结构。 第一牺牲氧化物层被形成在半导体衬底上，并且第一注入掩模被图案化成覆盖在第一牺牲氧化物层上以暴露与栅电极结构相邻的第一牺牲氧化物层的一部分。 电导率确定离子通过第一牺牲氧化物层注入到半导体衬底中。 在将导电性确定离子注入半导体衬底之后，去除第一注入掩模和第一牺牲氧化物层。

公开(公告)号：US10163933B1

公开(公告)日：2018-12-25

申请号：US15676529

申请日：2017-08-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Stefan Dünkel ,  Martin Trentzsch ,  Sven Beyer

IPC: H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L27/1159 ,  H01L27/11597 ,  H01L29/16 ,  H01L29/04 ,  H01L29/66 ,  H01L29/49 ,  H01L29/78 ,  H01L21/28 ,  H01L29/51

Abstract: Methods of forming a buffer layer to imprint ferroelectric phase in a ferroelectric layer and the resulting devices are provided. Embodiments include forming a substrate; forming a buffer layer over the substrate; forming a ferroelectric layer over the buffer layer; forming a channel layer over the ferroelectric layer; forming a gate oxide layer over a portion of the channel layer; and forming a gate over the gate oxide layer.

公开(公告)号：US20180158833A1

公开(公告)日：2018-06-07

申请号：US15883975

申请日：2018-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Martin Gerhardt

IPC: H01L27/11531 ,  H01L27/11534 ,  H01L27/11529 ,  H01L29/423 ,  H01L27/11519 ,  H01L27/11548 ,  H01L27/11524

CPC classification number: H01L27/11531 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11534 ,  H01L27/11548 ,  H01L29/42328 ,  H01L29/435

Abstract: A semiconductor structure includes a plurality of pairs of nonvolatile memory cells arranged in a row, an edge cell positioned adjacent to the pairs of nonvolatile memory cells, and first, second, third, and fourth gates. Each pair of nonvolatile memory cells includes first and second nonvolatile memory cells. The first and second gates extend across the first nonvolatile memory cells, the second gate partially overlapping the first gate, and the third and fourth gates extend across the second nonvolatile memory cells, the fourth gate partially overlapping the third gate. Each of the first, second, third, and fourth gates has an end portion that is positioned in the edge cell, and the edge cell includes a protection layer that is positioned over the end portions of the first, second, third, and fourth gates and covers an end face of the second and fourth gates.

公开(公告)号：US09972634B2

公开(公告)日：2018-05-15

申请号：US15234066

申请日：2016-08-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ralf Richter ,  Peter Krottenthaler ,  Martin Mazur

IPC: H01L27/115 ,  H01L27/11546 ,  H01L27/12 ,  H01L27/11521 ,  H01L29/78 ,  H01L29/788 ,  H01L29/423 ,  H01L29/161 ,  H01L29/10

CPC classification number: H01L27/11546 ,  H01L27/1207 ,  H01L29/161 ,  H01L29/42328

Abstract: A method of manufacturing a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried insulation layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried insulation layer, forming a first transistor device on and in the SOI substrate in a logic area of the SOI substrate, removing the semiconductor layer and the buried insulation layer from a memory area of the SOI substrate, forming a dielectric layer on the exposed semiconductor bulk substrate, forming a floating gate layer on the first dielectric layer, forming an insulating layer on the floating gate layer and forming a control gate layer on the insulating layer, wherein an upper surface of the floating gate layer is substantially at the same height level as an upper surface of the semiconductor layer remaining in the logic area.