公开(公告)号：US06516395B1

公开(公告)日：2003-02-04

申请号：US09626615

申请日：2000-07-27

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F1214

CPC分类号： G06F12/1491

摘要： A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to an MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether an MSR address is within a valid range. The MSR file may be divided into regions, with access granted based on a microprocessor being in a supervisory mode or a user mode.

摘要翻译： 用于控制对特定于模型的寄存器文件的特权分割地址空间的访问的系统和方法。 超标量微处理器包括多个型号特定寄存器（MSR）。 微处理器架构的各种实现之间的MSR不同。 MSR分配给MSR文件中的访问区域。 MSR文件的每个访问区域都被分配访问属性。 分配MSR使得MSR的接入区域和接入属性由MSR的地址定义。 通过将MSR的地址与微处理器的当前特权级别进行比较来控制对MSR的访问。 在一个实施例中，使用有效性检查电路来控制对MSR的访问。 如果尝试对当前微处理器权限级别无法访问的MSR进行访问，则拒绝对寄存器的访问，并生成异常。 在一个实施例中，可以使用地址检查器来验证MSR地址是否在有效范围内。 MSR文件可以被划分为区域，其中基于处于监控模式或用户模式的微处理器被准许访问。

公开(公告)号：US06378023B1

公开(公告)日：2002-04-23

申请号：US09481005

申请日：2000-01-10

申请人： David S. Christie ,  Brian C. Barnes

发明人： David S. Christie ,  Brian C. Barnes

IPC分类号： G06F1324

CPC分类号： G06F13/24 ,  G06F12/0875

摘要： An interrupt descriptor cache for a microprocessor is provided which is configured to store interrupt information associated with a plurality of interrupt vectors. Prior to fetching interrupt information from a main memory of a computer system, the microprocessor searches the interrupt descriptor cache. If the interrupt information is stored therein, the address of the interrupt service routine is formed from the stored interrupt information instead of fetching the interrupt information from main memory. The interrupt descriptor cache is additionally configured to monitory memory accesses for updates to the interrupt information stored therein. If a memory location storing interrupt information is updated, then the interrupt descriptor cache invalidates any storage locations which may be storing the information.

摘要翻译： 提供了一种用于微处理器的中断描述符缓存器，其被配置为存储与多个中断向量相关联的中断信息。 在从计算机系统的主存储器获取中断信息之前，微处理器搜索中断描述符缓存。 如果中断信息存储在其中，则中断服务程序的地址由存储的中断信息形成，而不是从主存储器取出中断信息。 中断描述符缓存另外被配置为对存储在其中的中断信息的更新的监控存储器访问。 如果更新存储中断信息的存储器位置，则中断描述符缓存使存储信息的任何存储位置无效。

公开(公告)号：US6151662A

公开(公告)日：2000-11-21

申请号：US982720

申请日：1997-12-02

申请人： David S. Christie ,  Brian D. McMinn ,  Stephan G. Meier ,  James K. Pickett

发明人： David S. Christie ,  Brian D. McMinn ,  Stephan G. Meier ,  James K. Pickett

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F12/12

CPC分类号： G06F9/30192 ,  G06F12/0862 ,  G06F12/0888 ,  G06F9/30047 ,  G06F9/345 ,  G06F9/383 ,  G06F2212/6028

摘要： A microprocessor assigns a data transaction type to each instruction. The data transaction type is based upon the encoding of the instruction, and indicates an access mode for memory operations corresponding to the instruction. The access mode may, for example, specify caching and prefetching characteristics for the memory operation. The access mode for each data transaction type is selected to enhance the speed of access by the microprocessor to the data, or to enhance the overall cache and prefetching efficiency of the microprocessor by inhibiting caching and/or prefetching for those memory operations. Instead of relying on data memory access patterns and overall program behavior to determine caching and prefetching operations, these operations are determined on an instruction-by-instruction basis. Additionally, the data transaction types assigned to different instruction encodings may be revealed to program developers. Program developers may use the instruction encodings (and instruction encodings which are assigned to a nil data transaction type causing a default access mode) to optimize use of processor resources during program execution.

摘要翻译： 微处理器为每个指令分配数据事务类型。 数据交易类型基于指令的编码，并且指示对应于指令的存储器操作的访问模式。 访问模式可以例如指定用于存储器操作的缓存和预取特性。 选择每个数据事务类型的访问模式以增强微处理器对数据的访问速度，或通过禁止对这些存储器操作的高速缓存和/或预取来增强微处理器的总体缓存和预取效率。 不依赖数据存储器访问模式和整体程序行为来确定高速缓存和预取操作，而是依据逐个指令来确定这些操作。 此外，分配给不同指令编码的数据事务类型可能会显示给程序开发人员。 程序开发人员可以使用指令编码（以及分配给导致默认访问模式的零数据事务类型的指令编码）来优化程序执行期间处理器资源的使用。

公开(公告)号：US6035386A

公开(公告)日：2000-03-07

申请号：US37436

申请日：1998-02-10

申请人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

发明人： David S. Christie ,  Scott A. White ,  Michael D. Goddard

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F9/26

CPC分类号： G06F9/382 ,  G06F9/30149 ,  G06F9/30152 ,  G06F9/30174 ,  G06F9/321 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A processor which includes a fetch program counter circuit and an execute program counter circuit is disclosed. The fetch program counter circuit provides less significant program counter value bits in addition to a fetch program counter value. The execute program counter circuit generates an execute program counter value using the less significant program counter value bits. The execute program counter circuit receives a plurality of less significant program counter bit values and selects a single less significant program counter bit value thus generating execute program counter values in a multiple pipeline processor.

摘要翻译： 公开了一种包括获取程序计数器电路和执行程序计数器电路的处理器。 获取程序计数器电路除了获取程序计数器值之外还提供不太重要的程序计数器值位。 执行程序计数器电路使用较不重要的程序计数器值位产生执行程序计数器值。 执行程序计数器电路接收多个不太重要的程序计数器位值，并且选择一个不太重要的程序计数器位值，从而在多流水线处理器中产生执行程序计数器值。

公开(公告)号：US5918056A

公开(公告)日：1999-06-29

申请号：US649246

申请日：1996-05-17

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24

摘要： A device and method that suspends segmentation addressing and prevents the modification of segmentation information (the segment registers and segment descriptors). By suspending segmentation addressing and preventing modification of segmentation information, the segmentation information does not have to be saved and restored by an interrupt. This reduces the overhead of the interrupt and allows the interrupt to be used in situations that are unfeasible for interrupts with larger overheads. When segmentation addressing is suspended, physical addresses are obtained from operands of the interrupt service routine instructions. Preventing the modification of the segmentation information allows operation of the processor to be transparently resumed after the completion of the interrupt.

摘要翻译： 一种暂停分段寻址并防止修改分段信息（段寄存器和段描述符）的设备和方法。 通过暂停分段寻址并防止分割信息的修改，分割信息不必被中断保存和恢复。 这减少了中断的开销，并允许中断在对于具有较大开销的中断不可行的情况下使用。 当分段寻址被暂停时，从中断服务程序指令的操作数获得物理地址。 防止分割信息的修改允许在完成中断之后透明地恢复处理器的操作。

公开(公告)号：US5822778A

公开(公告)日：1998-10-13

申请号：US886421

申请日：1997-07-01

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/02

CPC分类号： G06F9/30138 ,  G06F9/30116 ,  G06F9/3013 ,  G06F9/30185 ,  G06F9/342 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to control the selection of a bank of registers to use for the instruction operands. Each bank of registers includes the full complement of AMD 80x86 Series registers. Additional registers are available to a program other than the AMD 80x86 Series architecture specifies, but the instruction encoding is unchanged. Having more registers available to a program allows for more operands to be stored in the registers. Since registers are accessible in a shorter period of time than memory, operand access time is decreased.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来控制寄存器组的选择 用于指令操作数。 每个寄存器组包括AMD + Z 80x86系列寄存器的全套。 除AMD + Z 80x86系列架构外，其他寄存器可用于指定，但指令编码不变。 有更多的寄存器可用于程序允许更多的操作数存储在寄存器中。 由于寄存器在比内存更短的时间段内可访问，所以操作数访问时间减少。

公开(公告)号：US5768574A

公开(公告)日：1998-06-16

申请号：US914698

申请日：1997-08-19

申请人： Drew J. Dutton ,  David S. Christie

发明人： Drew J. Dutton ,  David S. Christie

IPC分类号： G06F9/318 ,  G06F9/32 ,  G06F9/38

CPC分类号： G06F9/30094 ,  G06F9/30185 ,  G06F9/34 ,  G06F9/3844

摘要： A microprocessor is provided which is configured to detect the presence of segment override prefixes in instruction code sequences being executed in flat memory mode, and to use the prefix value or the value stored in the associated segment register to selectively enable condition flag modification for instructions. An instruction which modifies the condition flags and a branch instruction intended to branch based on the condition flags set by the instruction may be separated by numerous instructions which do not modify the condition flags. When the branch instruction is decoded, the condition flags it depends on may already be available. In another embodiment of the present microprocessor, the segment register override bytes are used to select between multiple sets of condition flags. Multiple conditions may be retained by the microprocessor for later examination. Conditions which a program utilizes multiple times in a program may be maintained while other conditions may be generated and utilized.

摘要翻译： 提供了微处理器，其被配置为检测在平面存储器模式下执行的指令代码序列中是否存在段超越前缀，并且使用前缀值或存储在相关联的段寄存器中的值来选择性地启用用于指令的条件标志修改。 根据指令设定的条件标志修改条件标志和分支指令的指令可以被不修改条件标志的许多指令分开。 当分支指令被解码时，它所依赖的条件标志可能已经可用。 在本微处理器的另一实施例中，段寄存器覆盖字节用于在多组条件标志之间进行选择。 微处理器可以保留多个条件供以后检查。 在程序中利用多次的程序的条件可以被保持，而可以产生和利用其他条件。

公开(公告)号：US5632023A

公开(公告)日：1997-05-20

申请号：US252029

申请日：1994-06-01

申请人： Scott A. White ,  David S. Christie ,  Michael D. Goddard

发明人： Scott A. White ,  David S. Christie ,  Michael D. Goddard

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F9/30094 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： A superscalar microprocessor is provided with a reorder buffer for storing the speculative state of the microprocessor and a register file for storing the real state of the microprocessor. A flags register stores the real state of flags that are updated by flag modifying instructions which are executed by the functional units of the microprocessor. To enhance the performance of the microprocessor with respect to conditional branching instructions, the reorder buffer includes a flag storage area for storing flags that are updated by flag modifying instructions. The flags are renamed to make possible the earlier execution of branch instructions which depend on flag modifying instructions. If a flag is not yet determined, then a flag tag is associated with the flag storage area in place of that flag until the actual flag value is determined. A flag operand bus and a flag tag bus are provided between the flag storage area and the branching functional unit so that the requested flag or flag tags are provided to instructions which are executed in the branching functional unit.

摘要翻译： 超标量微处理器设置有用于存储微处理器的推测状态的重排序缓冲器和用于存储微处理器的实际状态的寄存器文件。 标志寄存器存储由微处理器的功能单元执行的标志修改指令更新的标志的实际状态。 为了提高微处理器相对于条件转移指令的性能，重排序缓冲器包括一个标志存储区域，用于存储通过标志修改指令更新的标志。 这些标志被重命名，以便能够更早地执行依赖于标志修改指令的分支指令。 如果尚未确定标志，则标志标签与标志存储区域相关联，而不是该标志，直到确定了实际标志值。 在标志存储区域和分支功能单元之间提供标志操作数总线和标志标签总线，使得所请求的标志或标志标签提供给在分支功能单元中执行的指令。

公开(公告)号：US08407455B2

公开(公告)日：2013-03-26

申请号：US12510893

申请日：2009-07-28

申请人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

发明人： David S. Christie ,  Michael P. Hohmuth ,  Stephan Diestelhorst

IPC分类号： G06F9/00

CPC分类号： G06F9/466 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/468 ,  G06F9/52

摘要： A computer-implemented method and article of manufacture is disclosed for enabling computer programs utilizing hardware transactional memory to safely interact with code utilizing traditional locks. A thread executing on a processor of a plurality of processors in a shared-memory system may initiate transactional execution of a section of code, which includes a plurality of access operations to the shared-memory, including one or more to locations protected by a lock. Before executing any operations accessing the location associated with the lock, the thread reads the value of the lock as part of the transaction, and only proceeds if the lock is not held. If the lock is acquired by another thread during transactional execution, the processor detects this acquisition, aborts the transaction, and attempts to re-execute it.

摘要翻译： 公开了一种计算机实现的方法和制造物品，用于使得利用硬件事务存储器的计算机程序能够利用传统的锁来安全地与代码交互。 在共享存储器系统中的多个处理器的处理器上执行的线程可以发起一段代码的事务执行，该部分包括对共享存储器的多个访问操作，包括一个或多个到由锁定保护的位置 。 在执行访问与锁相关联的位置的任何操作之前，线程将作为事务的一部分读取锁的值，并且只有在不保持锁定的情况下才会继续。 如果在事务执行期间锁被另一个线程获取，则处理器检测到该获取，中止事务并尝试重新执行该事务。

公开(公告)号：US08195917B2

公开(公告)日：2012-06-05

申请号：US12496335

申请日：2009-07-01

申请人： Michael P. Hohmuth ,  Uwe M. Dannowski ,  Sebastian Biemueller ,  David S. Christie ,  Stephan Diestelhorst ,  Thomas Friebel

发明人： Michael P. Hohmuth ,  Uwe M. Dannowski ,  Sebastian Biemueller ,  David S. Christie ,  Stephan Diestelhorst ,  Thomas Friebel

IPC分类号： G06F12/10

CPC分类号： G06F12/1009 ,  G06F12/1027 ,  G06F2212/652

摘要： A processor including a virtual memory paging mechanism. The virtual memory paging mechanism enables an operating system operating on the processor to use pages of a first size and a second size, the second size being greater than the first size. The mechanism further enables the operating system to use superpages including two or more contiguous pages of the first size. The size of a superpage is less than the second size. The processor further includes a page table having a separate entry for each of the pages included in each superpage. The operating system accesses each superpage using a single virtual address. The mechanism interprets a single entry in a translation lookaside buffer TLB as referring to a region of memory comprising a set of pages that correspond to a superpage in response to detecting a superpage enable indicator associated with the entry in the TLB is asserted.

摘要翻译： 一种包括虚拟存储器寻呼机构的处理器。 虚拟存储器分页机构使得在处理器上操作的操作系统能够使用具有第一尺寸和第二尺寸的页面，第二尺寸大于第一尺寸。 该机制进一步使得操作系统能够使用包括第一尺寸的两个或更多个连续页面的超级页面。 超级页面的大小小于第二个大小。 处理器还包括页表，其具有用于每个超级页面中包括的每个页面的单独条目。 操作系统使用单个虚拟地址访问每个超级页面。 该机制将翻译后备缓存器TLB中的单个条目解释为响应于检测到与TLB中的条目相关联的超级页面使能指示符被断言的引用包括与超级页面相对应的页面的存储器区域。