公开(公告)号：US20160012952A1

公开(公告)日：2016-01-14

申请号：US14864191

申请日：2015-09-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hanyi Ding ,  Anthony K. Stamper

IPC: H01F27/00 ,  H01F27/28

CPC classification number: H01F27/006 ,  H01F17/0013 ,  H01F27/2804 ,  H01F2017/004 ,  H01F2027/2819

Abstract: Various embodiments include inductor structures including at least one air gap for reducing capacitance between windings in the inductor structure. One embodiment includes an inductor structure having: a substrate; an insulation layer overlying the substrate; a conductive winding overlying the substrate within the insulation layer, the conductive winding wrapped around itself to form a plurality of turns substantially concentric about a central axis; an insulating structural support containing an air gap between the conductive winding and the insulation layer, the insulating structural support at least one of under, over or surrounding the plurality of turns of the conductive winding or between adjacent turns in the conductive winding; and at least one insulation pocket located radially inside a radially innermost turn in the plurality of turns with respect to the central axis.

公开(公告)号：US11527432B2

公开(公告)日：2022-12-13

申请号：US17086925

申请日：2020-11-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  Ian McCallum-Cook ,  Siva P. Adusumilli

IPC: H01L21/763 ,  H01L29/06 ,  H01L27/12 ,  H01L21/762 ,  H01L21/324 ,  H01L21/84 ,  H01L21/265 ,  H01L21/74 ,  H01L29/32 ,  H01L21/02 ,  H01L27/06 ,  H01L29/10

Abstract: Structures with altered crystallinity beneath semiconductor devices and methods associated with forming such structures. Trench isolation regions surround an active device region composed of a single-crystal semiconductor material. A first non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. A second non-single-crystal layer is arranged beneath the trench isolation regions and the active device region. The first non-single-crystal layer is arranged between the second non-single-crystal layer and the active device region.

公开(公告)号：US20210043624A1

公开(公告)日：2021-02-11

申请号：US16534361

申请日：2019-08-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Siva P. Adusumilli ,  Julien Frougier ,  Ruilong Xie ,  Anthony K. Stamper

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L29/04

Abstract: Structures with altered crystallinity and methods associated with forming such structures. A semiconductor layer has a first region containing polycrystalline semiconductor material, defects, and atoms of an inert gas species. Multiple fins are arranged over the first region of the semiconductor layer. The structure may be formed by implanting the semiconductor layer with inert gas ions to modify a crystal structure of the semiconductor layer in the first region and a second region between the first region and a top surface of the semiconductor layer. An annealing process is used to convert the first region of the semiconductor layer to a polycrystalline state and the second region of the semiconductor layer to a monocrystalline state. The fins are patterned from the second region of the semiconductor layer and another semiconductor layer epitaxially grown over the second region of the semiconductor layer.

公开(公告)号：US10916642B2

公开(公告)日：2021-02-09

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor Jain ,  Anthony K. Stamper ,  Steven M. Shank ,  John J. Pekarik

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US10903207B2

公开(公告)日：2021-01-26

申请号：US16258714

申请日：2019-01-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Siva P. Adusumilli

IPC: H01L27/06 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/84 ,  H01L49/02 ,  H01L29/08 ,  H01L29/45 ,  H01L29/06 ,  H01L27/12 ,  H01L27/105 ,  H01L21/02 ,  H01L21/265 ,  H01L27/088

Abstract: Disclosed is an integrated circuit (IC) formation method, wherein trenches are formed within a semiconductor layer to define semiconductor mesa(s). Instead of immediately filling the trenches with an isolation material and performing a planarizing process to complete the STI regions prior to device formation, the method initially only form sidewall spacers within the trenches on the exposed sidewalls of the semiconductor mesa(s). After the sidewall spacers are formed, device(s) (e.g., field effect transistor(s), silicon resistor(s), etc.) are formed using the semiconductor mesa(s) and, optionally, additional device(s) (e.g., polysilicon resistor(s)) can be formed within the trenches between adjacent semiconductor mesas. Subsequently, middle of the line (MOL) dielectrics (e.g., a conformal etch stop layer and a blanket interlayer dielectric (ILD) layer) are deposited over the device(s), thereby filling any remaining space within the trenches and completing the STI regions. Also disclosed is an IC structure formed using the method.

公开(公告)号：US10818763B1

公开(公告)日：2020-10-27

申请号：US16405368

申请日：2019-05-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  Michel J. Abou-Khalil ,  Siva P. Adusumilli

IPC: H01L29/423 ,  H01L21/8234 ,  H01L29/45 ,  H01L27/088

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A first gate electrode has a first plurality of segments arranged in series to define a first non-rectilinear chain. A second gate electrode is arranged adjacent to the first gate electrode. The second gate electrode includes a second plurality of segments arranged in series to define a second non-rectilinear chain. A source/drain region is laterally arranged between the first gate electrode and the second gate electrode.

公开(公告)号：US20200235729A1

公开(公告)日：2020-07-23

申请号：US16252007

申请日：2019-01-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony K. Stamper ,  Vibhor Jain

IPC: H03K17/14 ,  G05D23/19 ,  G05D23/24 ,  H01C7/04 ,  G01K3/00

Abstract: One illustrative device includes, among other things, an active device comprising a first terminal, a first bias resistor connected to the first terminal, and a first resistor comprising a first phase transition material connected in parallel with the first bias transistor, wherein the first phase transition material exhibits a first low conductivity phase for temperatures less than a first phase transition temperature and a first high conductivity phase for temperatures greater than the first phase transition temperature.

公开(公告)号：US10411107B2

公开(公告)日：2019-09-10

申请号：US15693537

申请日：2017-09-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Laura J. Schutz ,  Anthony K. Stamper ,  Siva P. Adusumilli ,  Joshua F. Dillon

IPC: H01L29/49 ,  H01L29/417 ,  H01L29/423 ,  H01L21/3205 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L21/762 ,  H01L21/28

Abstract: A method may include forming a transistor on a substrate, the transistor including a gate, and forming a sacrificial spacer extending along an entirety of a thickness of the gate. A via layer is then formed over/about the gate. The sacrificial spacer is at least partially removed, leaving an air vent opening. An airgap spacer is formed in the dielectric layer by depositing another dielectric layer to close off the air vent opening. The airgap spacer is coincident with at least one sidewall of the gate and extends along an entirety of a thickness of the gate. Gate airgaps may also be provided over the gate. Other embodiments extend the gate and airgap spacer the full thickness of the dielectric layer thereabout. Other embodiments extend the airgap spacer over the gate.

公开(公告)号：US20190267304A1

公开(公告)日：2019-08-29

申请号：US16405325

申请日：2019-05-07

Applicant: GlobalFoundries Inc.

Inventor： Hanyi Ding ,  Vibhor Jain ,  Alvin J. Joseph ,  Anthony K. Stamper

IPC: H01L23/367 ,  H01L29/732 ,  H01L29/66 ,  H01L29/08 ,  H01L21/48 ,  H01L29/417

Abstract: Chip packages and methods of forming a chip package. The chip package includes a power amplifier and a thermal pathway structure configured to influence transport of heat energy. The power amplifier includes a first emitter finger and a second emitter finger having at least one parameter that is selected based upon proximity to the thermal pathway structure.

公开(公告)号：US10243047B2

公开(公告)日：2019-03-26

申请号：US15372929

申请日：2016-12-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/10 ,  H01L29/06 ,  H01L23/66 ,  H01L21/762 ,  H01L29/78 ,  H01L25/18 ,  H01L21/764 ,  H01L21/8234

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to active and passive radio frequency (RF) components with deep trench isolation structures and methods of manufacture. The structure includes a bulk high resistivity wafer with a deep trench isolation structure having a depth deeper than a maximum depletion depth at worst case voltage bias difference between devices which are formed on the bulk high resistivity wafer.