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    Double bias memristive dot product engine for vector processing
    23.
    发明授权
    Double bias memristive dot product engine for vector processing 有权

    公开(公告)号：US10109348B2

    公开(公告)日：2018-10-23

    申请号：US15522364

    申请日：2014-10-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  Jianhua Yang ,  John Paul Strachan ,  Ning Ge

    IPC: G11C13/00 ,  G06F17/16

    Abstract: A double bias dot-product engine for vector processing is described. The dot product engine includes a crossbar array having N×M memory elements to store information corresponding to values contained in an N×M matrix, each memory element being a memristive storage device. First and second vector input registers including N voltage inputs, each voltage input corresponding to a value contained in a vector having N×1 values. The vector input registers are connected to the crossbar array to supply voltage inputs to each of N row electrodes at two locations along the electrode. A vector output register is also included to receive voltage outputs from each of M column electrodes.

    Asymmetrically selecting memory elements
    24.
    发明授权
    Asymmetrically selecting memory elements 有权

    公开(公告)号：US09934849B2

    公开(公告)日：2018-04-03

    申请号：US15320779

    申请日：2014-07-25

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Kyung Min Kim ,  Jianhua Yang ,  Zhiyong Li

    IPC: G11C11/00 ,  G11C13/00

    CPC classification number: G11C13/003 ,  G11C2013/0073 ,  G11C2213/72

    Abstract: A system for asymmetrically selecting a memory element is described. The system includes a number of memory cells in a crossbar array. Each memory cell includes a memory element to store information. The memory element is defined as an intersection between a column electrode and a row electrode of the crossbar array. Each memory cell also includes a selector to select a target memory element by relaying a first selecting voltage to a column electrode that corresponds to the target memory element and relaying a second selecting voltage to a row electrode that corresponds to the target memory element. The system also includes a controller to pass a first standing voltage to column electrodes of the crossbar array and to pass a second standing voltage to row electrodes of the crossbar array. The first standing voltage is different than the second standing voltage.

    Memory controllers
    26.
    发明授权
    Memory controllers 有权

    公开(公告)号：US09911490B2

    公开(公告)日：2018-03-06

    申请号：US15314687

    申请日：2014-05-30

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Ning Ge ,  Jianhua Yang ,  Frederick Perner ,  Janice H. Nickel

    IPC: G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C2013/0045 ,  G11C2213/77

    Abstract: A memory controller includes a voltage control module that operates to isolate a target memristor of a memory crossbar array. The voltage control module applies a column voltage to a column line coupled to the target memristor, applies a first row voltage to all row lines not coupled to the target memristor and a second row voltage to a row line coupled to the target memristor, and senses a current through the target memristor to determine a state of the target memristor. The memory crossbar array includes a plurality of column lines, a plurality of row lines, a plurality of memristors, and a plurality of shorting switches. Each memristor is coupled between a unique combination of one column line and one row line. Each shorting switch has a high impedance resistor and a low impedance transistor, and each shorting switch is coupled to an end of a unique row line.

    Resistive elements to operate as a matrix of probabilities
    27.
    发明授权
    Resistive elements to operate as a matrix of probabilities 有权

    公开(公告)号：US09847124B2

    公开(公告)日：2017-12-19

    申请号：US15500500

    申请日：2015-04-23

    Applicant: Hewlett Packard Enterprise Development LP

    Inventor： Miao Hu ,  John Paul Strachan ,  Ning Ge ,  Jianhua Yang

    IPC: G11C13/00 ,  G06N7/00 ,  G06F17/18

    CPC classification number: G11C13/0021 ,  G06F7/588 ,  G06F17/18 ,  G06G7/122 ,  G06N7/005

    Abstract: An example apparatus includes a crossbar array of signal lines and control lines. The example apparatus also includes an input controller in circuit with the control lines. The input control is to select one of the control lines. The example apparatus also includes first resistive elements connected between corresponding ones of the control lines and corresponding ones of the signal lines. The first resistive elements have first conductances set to operate as a matrix of probabilities that define a fixed transition kernel of a Markov Chain. The example apparatus also includes second resistive elements in circuit with the signal lines. The second resistive elements have second conductances set to select one of the signal lines exclusive of others of the signal lines based on a subset of the probabilities in the matrix of the probabilities.

    NONLINEAR DIELECTRIC STACK CIRCUIT ELEMENT
    29.
    发明申请
    NONLINEAR DIELECTRIC STACK CIRCUIT ELEMENT 审中-公开
    非线性电介质电路元件

    公开(公告)号：US20160351802A1

    公开(公告)日：2016-12-01

    申请号：US15111515

    申请日：2014-01-30

    Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

    Inventor： Warren Jackson ,  Gary Gibson ,  R. Stanley Williams ,  Jianhua Yang

    IPC: H01L45/00 ,  G11C13/00

    CPC classification number: H01L45/12 ,  G11C13/003 ,  H01L27/2418 ,  H01L45/00

    Abstract: A nonlinear dielectric stack circuit element includes a first layer of material having a first dielectric constant; a second layer of material having a second dielectric constant; and a third layer of material sandwiched between the first layer of material and the second layer of material and having a third dielectric constant. The third dielectric constant has a value less than the first dielectric constant and the second dielectric constant.

    Abstract translation: 非线性介质堆叠电路元件包括具有第一介电常数的第一材料层; 具有第二介电常数的第二材料层; 以及夹在所述第一材料层和所述第二材料层之间并具有第三介电常数的第三材料层。 第三介电常数的值小于第一介电常数和第二介电常数。

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