公开(公告)号：US06235651B1

公开(公告)日：2001-05-22

申请号：US09395952

申请日：1999-09-14

申请人： Martin Schrems ,  Helmut Horst Tews

发明人： Martin Schrems ,  Helmut Horst Tews

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

摘要翻译： 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

公开(公告)号：US08003470B2

公开(公告)日：2011-08-23

申请号：US11224825

申请日：2005-09-13

申请人： Helmut Horst Tews ,  Andre Schenk

发明人： Helmut Horst Tews ,  Andre Schenk

IPC分类号： H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L27/088 ,  H01L27/1203 ,  H01L29/66477 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7834

摘要： In a method for forming a semiconductor device, a gate electrode is formed over a semiconductor body (e.g., bulk silicon substrate or SOI layer). The gate electrode is electrically insulated from the semiconductor body. A first sidewall spacer is formed along a sidewall of the gate electrode. A sacrificial sidewall spacer is formed adjacent the first sidewall spacer. The sacrificial sidewall spacer and the first sidewall spacer overlying the semiconductor body. A planarization layer is formed over the semiconductor body such that a portion of the planarization layer is adjacent the sacrificial sidewall spacer. The sacrificial sidewall spacer can then be removed and a recess etched in the semiconductor body. The recess is substantially aligned between the first sidewall spacer and the portion of the planarization layer. A semiconductor material (e.g., SiGe or SiC) can then be formed in the recess.

摘要翻译： 在形成半导体器件的方法中，在半导体本体（例如体硅衬底或SOI层）上形成栅电极。 栅电极与半导体本体电绝缘。 沿着栅电极的侧壁形成第一侧壁间隔物。 邻近第一侧壁间隔件形成牺牲侧壁间隔物。 牺牲侧壁间隔件和覆盖半导体本体的第一侧壁间隔件。 平坦化层形成在半导体本体上，使得平坦化层的一部分与牺牲侧壁间隔物相邻。 然后可以去除牺牲侧壁间隔物并在半导体本体中蚀刻凹陷。 所述凹部基本上在所述第一侧壁间隔物和所述平坦化层的所述部分之间对准。 然后可以在凹部中形成半导体材料（例如，SiGe或SiC）。

公开(公告)号：US20090141424A1

公开(公告)日：2009-06-04

申请号：US11947591

申请日：2007-11-29

申请人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

发明人： Hans-Joachim Barth ,  Erwin Ruderer ,  Alexander Von Glasow ,  Philipp Riess ,  Erdem Kaltalioglu ,  Peter Baumgartner ,  Thomas Benetik ,  Helmut Horst Tews

IPC分类号： H01G4/33 ,  H01G4/00

CPC分类号： H01L27/0805 ,  H01L23/5223 ,  H01L2924/0002 ,  H01L2924/00

摘要： Semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, a capacitor plate includes a plurality of first parallel conductive members, and a plurality of second parallel conductive members disposed over the plurality of first parallel conductive members. A first base member is coupled to an end of the plurality of first parallel conductive members, and a second base member is coupled to an end of the plurality of second parallel conductive members. A connecting member is disposed between the plurality of first parallel conductive members and the plurality of second parallel conductive members, wherein the connecting member includes at least one elongated via.

摘要翻译： 公开了半导体器件及其制造方法。 在一个实施例中，电容器板包括多个第一平行导电构件，以及设置在多个第一平行导电构件上的多个第二平行导电构件。 第一基座构件联接到多个第一平行导电构件的端部，并且第二基座构件联接到多个第二平行导电构件的端部。 连接构件设置在多个第一平行导电构件和多个第二平行导电构件之间，其中连接构件包括至少一个细长通孔。

公开(公告)号：US06905944B2

公开(公告)日：2005-06-14

申请号：US10249798

申请日：2003-05-08

申请人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

发明人： Michael Patrick Chudzik ,  Irene McStay ,  Helmut Horst Tews ,  Porshia Shane Wrschka

IPC分类号： H01L21/76 ,  H01L21/8242

CPC分类号： H01L27/1087

摘要： A method for fabricating a deep trench etched into a semiconductor substrate is provided by the present invention. The trench is divided into an upper portion and a lower portion and the method allows for the lower portion to be processed differently from the upper portion. After the trench is etched into the semiconductor substrate, a nitride layer is formed over a sidewall of the trench. A layer of oxide is then formed over the nitride layer. A filler material is then deposited and recessed to cover the oxide layer in the lower portion of the trench, followed by the removal of the oxide layer from the upper portion of the trench above the filler material. Once the oxide layer is removed from the upper portion of the trench, the filler material can also be removed, while allowing the oxide layer and the nitride layer to remain in the lower portion of the trench. Silicon is selectively deposited on the exposed nitride layer in the upper portion of the trench. The oxide layer and the nitride layer is then removed from the lower portion. Finally, the lower portion of the trench is processed selectively to nitride, e.g. by one or more capacitor forming processes, and then the upper portion of the trench is processed.

摘要翻译： 通过本发明提供了蚀刻成半导体衬底的深沟槽的制造方法。 沟槽被分成上部和下部，并且该方法允许下部被加工成与上部不同。 在沟槽被蚀刻到半导体衬底中之后，在沟槽的侧壁上形成氮化物层。 然后在氮化物层上形成一层氧化物。 然后将填料材料沉积并凹入以覆盖沟槽下部的氧化物层，然后从填料材料上方的沟槽上部除去氧化物层。 一旦从沟槽的上部去除氧化物层，也可以去除填充材料，同时允许氧化物层和氮化物层保留在沟槽的下部。 选择性地将硅沉积在沟槽上部的暴露的氮化物层上。 然后从下部去除氧化物层和氮化物层。 最后，沟槽的下部被选择性地加工成氮化物，例如。 通过一个或多个电容器形成工艺，然后处理沟槽的上部。

公开(公告)号：US06620724B1

公开(公告)日：2003-09-16

申请号：US10142518

申请日：2002-05-09

申请人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

发明人： Uwe Schroeder ,  Helmut Horst Tews ,  Irene McStay ,  Manfred Hauf ,  Matthias Goldbach ,  Bernhard Sell ,  Harald Seidl ,  Dirk Schumann ,  Rajarao Jammy ,  Joseph F. Shepard, Jr. ,  Jean-Marc Rousseau

IPC分类号： H01L214763

CPC分类号： H01L28/60 ,  H01L27/10861

摘要： Semiconductor devices having deep trenches with fill material therein having low resistivity are provided along with methods of fabricating such semiconductor devices.

摘要翻译： 提供其具有低电阻率的具有低填充材料的深沟槽的半导体器件以及制造这种半导体器件的方法。

公开(公告)号：US06613642B2

公开(公告)日：2003-09-02

申请号：US10016075

申请日：2001-12-13

申请人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

发明人： Stephen Rahn ,  Irene McStay ,  Helmut Horst Tews ,  Uwe Schroeder ,  Stephan Kudelka ,  Rajarao Jammy

IPC分类号： H01L2120

CPC分类号： H01L27/1087 ,  H01L28/84 ,  H01L28/90

摘要： A method for increasing the surface area of an original surface in a semiconductor device is disclosed. In an exemplary embodiment of the invention, the method includes forming a layered mask upon the original surface, the layered mask including a masking layer thereatop having a varying thickness. An isotropic etch is then applied to the layered mask, which isotropic etch further removes exposed portions of the original surface as the layered mask is removed. Thereby, the isotropic etch enhances the non-uniformity of the masking layer and creates a non-uniformity in planarity of the original surface.

摘要翻译： 公开了一种用于增加半导体器件中原始表面的表面积的方法。 在本发明的示例性实施例中，该方法包括在原始表面上形成分层掩模，该分层掩模包括具有变化厚度的掩模层。 然后将各向同性蚀刻施加到分层掩模，其中各向同性蚀刻在去除层状掩模时进一步去除原始表面的暴露部分。 因此，各向同性蚀刻增强了掩模层的不均匀性并且产生了原始表面的平坦度的不均匀性。

公开(公告)号：US06559002B1

公开(公告)日：2003-05-06

申请号：US10032041

申请日：2001-12-31

申请人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

发明人： Stephan Kudelka ,  Helmut Horst Tews ,  Stephen Rahn ,  Irene McStay ,  Uwe Schroeder

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L28/84 ,  Y10S438/964

摘要： In a process for making a DT DRAM structure, the improvement of providing a surface area enhanced DT below the collar region and node capacitance that does not shrink with decreasing groundrule/cell size, comprising: a) providing a semiconductor substrate having a collar region and an adjacent region below the collar region, the collar region having SiO deposited thereon; b) depositing a SiN liner on said collar region and on the region below the collar; c) depositing a layer of a-Si on the SiN liner to form a micromask; d) subjecting the structure from step c) to an anneal/oxidation step under a wet environment at a sufficient temperature to form a plurality of oxide dot hardmasks; e) subjecting the SiN liner to an etch selective to SiO; f) subjecting the structure from step e) to a Si transfer etch using a chemical dry etch (CDE) selective to SiO to create rough Si surface; g) stripping SiO and the SiN; and forming a node and collar deposition.

摘要翻译： 在制造DT DRAM结构的过程中，提高在轴环区域之下提供的表面积增强的DT和不随着降低的底层/单元尺寸而缩小的节点电容，包括：a）提供具有轴环区域和 在轴环区域下方的相邻区域，其上沉积有SiO的轴环区域; b）在所述轴环区域和轴环下方的区域上沉积SiN衬垫; c）在SiN衬套上沉积a-Si层以形成 微型掩模; d）使所述步骤c）的结构在潮湿环境下在足够的温度下进行退火/氧化步骤，以形成多个氧化物点硬掩模; e）使所述SiN衬底对SiO选择性蚀刻; f） 使用对SiO选择性的化学干蚀刻（CDE）来产生粗糙的Si表面的步骤e）到Si转移蚀刻的结构; g）剥离SiO和SiN; 并形成一个节点和项圈沉积。

公开(公告)号：US06537926B1

公开(公告)日：2003-03-25

申请号：US09638309

申请日：2000-08-14

申请人： Martin Schrems ,  Helmut Horst Tews

发明人： Martin Schrems ,  Helmut Horst Tews

IPC分类号： H01L2131

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/31662

摘要： A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.g., in oxygen and/or water vapor, at the high oxidizing temperature to increase uniformly the oxide layer to a selective final thickness, e.g., of 20-100 angstroms, whereupon the resultant uniform final thickness oxide layer-containing wafer is recovered from the furnace.

摘要翻译： 提供了两步逐步热氧化工艺以改善半导体晶片制造中薄氧化物层的厚度均匀性。 诸如硅的半导体晶片，具有在其上形成氧化物层但基本上不含氧化物层的表面，例如在室温下被加载到维持在低负载温度的氧化炉中，例如 ，400-600℃，并且将晶片温度调节至低氧化温度，例如400-600℃，同时晶片处于惰性，例如氮气氛下。 然后将晶片在低氧化温度下进行初始氧化，例如在干燥的氧气中，以在表面上形成均匀的初始厚度氧化物，例如二氧化硅，例如至多10埃的层，之后 炉温升高到高的氧化温度，例如700-1200℃，同时晶片处于惰性气氛。 接着在高氧化温度下将晶片进行最终氧化，例如在氧气和/或水蒸气中，以将氧化物层均匀地增加至选择性最终厚度，例如20-100埃，由此得到均匀的最终厚度 从炉中回收含氧化物层的晶片。

公开(公告)号：US06475859B1

公开(公告)日：2002-11-05

申请号：US09593287

申请日：2000-06-13

申请人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

发明人： Helmut Horst Tews ,  Brian S. Lee ,  Joachim Hoepfner

IPC分类号： H01L218242

CPC分类号： H01L27/1087 ,  H01L21/2236 ,  H01L28/84

摘要： A method of doping trench sidewall and hemispherical-grained silicon in deep trench cells to increase surface area and storage capacitance while avoiding deformation of trenches and hemispherical-grained silicon, comprising: a) Etching a deep trench structure by reactive ion etching; b) Forming a LOCOS collar in an upper portion of the trench over a conformal layer of a silicon containing material, the collar leaving a lower portion of the trench exposed; c) Depositing a film of hemispherical-grained silicon (HSG-Si) at sidewalls of the deep trench; d) Plasma doping the hemispherical-grained silicon; and e) Depositing a node dielectric and filling the trench with polysilicon.

摘要翻译： 一种在深沟槽单元中掺杂沟槽侧壁和半球晶硅的方法，以增加表面面积和存储电容，同时避免沟槽和半球晶硅的变形，包括：a）通过反应离子蚀刻蚀刻深沟槽结构; b）形成 在包含硅的材料的保形层上的沟槽上部的LOCOS环，所述套环暴露出沟槽的下部; c）在半导体衬底的侧壁处沉积半球形硅（HSG-Si）的膜 深沟槽; d）等离子体掺杂半球形硅; 安装）沉积节点电介质并用多晶硅填充沟槽。

公开(公告)号：US6159874A

公开(公告)日：2000-12-12

申请号：US427991

申请日：1999-10-27

申请人： Helmut Horst Tews ,  Brian Lee

发明人： Helmut Horst Tews ,  Brian Lee

IPC分类号： H01L21/20 ,  H01L21/02 ,  H01L21/265 ,  H01L21/318 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L27/10861

摘要： A method of manufacturing a capacitor is provided where at least a portion of a silicon surface is amorphized. The amorphized silicon surface is then subjected to an annealing process to form hemispherical silicon grains (HSG) from the amorphized portion of the silicon surface to form at least a portion of a first electrode of the capacitor. A capacitor dielectric is then formed over the hemispherical silicon grains. A second electrode is then formed over the capacitor dielectric.

摘要翻译： 提供一种制造电容器的方法，其中硅表面的至少一部分是非晶化的。 然后对非晶化硅表面进行退火处理以从硅表面的非晶化部分形成半球状硅晶粒（HSG），以形成电容器的第一电极的至少一部分。 然后在半球形硅晶粒上形成电容器电介质。 然后在电容器电介质上形成第二电极。