公开(公告)号：US08975118B2

公开(公告)日：2015-03-10

申请号：US13701277

申请日：2011-04-13

Applicant: Julian Gonska ,  Jens Frey ,  Heribert Weber ,  Eckhard Graf ,  Roman Schlosser

Inventor： Julian Gonska ,  Jens Frey ,  Heribert Weber ,  Eckhard Graf ,  Roman Schlosser

IPC: H01L27/088 ,  H01L23/48 ,  B81C1/00 ,  H01L21/768

CPC classification number: H01L23/481 ,  B81B2203/033 ,  B81B2207/095 ,  B81C1/00095 ,  H01L21/76837 ,  H01L23/04 ,  H01L2224/48463 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An advantageous method and system for realizing electrically very reliable and mechanically extremely stable vias for components whose functionality is realized in a layer construction on a conductive substrate. The via (Vertical Interconnect Access), which is led to the back side of the component and which is used for the electrical contacting of functional elements realized in the layer construction, includes a connection area in the substrate that extends over the entire thickness of the substrate and is electrically insulated from the adjoining substrate by a trench-like insulating frame likewise extending over the entire substrate thickness. According to the present system, the trench-like insulating frame is filled up with an electrically insulating polymer.

Abstract translation: 一种有利的方法和系统，用于实现电气非常可靠和机械上非常稳定的通孔，用于在导电基底上的层结构中实现其功能的部件。 被引导到部件的背面并用于在层结构中实现的功能元件的电接触的通孔（垂直互连访问）包括在基板中的连接区域，该连接区域在整个厚度 并且通过类似于整个基板厚度延伸的沟槽状绝缘框架与邻接的基板电绝缘。 根据本系统，沟槽状绝缘框架填充有电绝缘聚合物。

公开(公告)号：US20140110800A1

公开(公告)日：2014-04-24

申请号：US14058806

申请日：2013-10-21

Applicant: Johannes CLASSEN ,  Axel Franke ,  Jens Frey ,  Heribert Weber ,  Frank Fischer ,  Patrick Wellner

Inventor： Johannes CLASSEN ,  Axel Franke ,  Jens Frey ,  Heribert Weber ,  Frank Fischer ,  Patrick Wellner

IPC: B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00015 ,  B81B3/0018 ,  B81B7/0058

Abstract: A manufacturing method for a cap, for a hybrid vertically integrated component having a MEMS component a relatively large cavern volume having a low cavern internal pressure, and a reliable overload protection for the micromechanical structure of the MEMS component. A cap structure is produced in a flat cap substrate in a multistep anisotropic etching, and includes at least one mounting frame having at least one mounting surface and a stop structure, on the cap inner side, having at least one stop surface, the surface of the cap substrate being masked for the multistep anisotropic etching with at least two masking layers made of different materials, and the layouts of the masking layers and the number and duration of the etching steps being selected so that the mounting surface, the stop surface, and the cap inner side are situated at different surface levels of the cap structure.

Abstract translation: 一种用于具有MEMS部件的混合垂直集成部件的盖的制造方法，具有较低的洞穴内部压力的相对较大的洞穴体积以及用于MEMS部件的微机械结构的可靠的过载保护。 在多步骤各向异性蚀刻中，在平盖基板中制造盖结构，并且包括至少一个安装框架，该安装框架具有至少一个安装表面和止动结构，在盖内侧具有至少一个止动表面， 掩模基板被掩模用于具有由不同材料制成的至少两个掩模层的多步各向异性蚀刻，并且选择掩模层的布局以及蚀刻步骤的数量和持续时间，使得安装表面，止动表面和 帽内侧位于帽结构的不同表面水平处。

公开(公告)号：US08558327B2

公开(公告)日：2013-10-15

申请号：US12451033

申请日：2008-02-29

Applicant: Kathrin Knese ,  Heribert Weber ,  Simon Armbruster

Inventor： Kathrin Knese ,  Heribert Weber ,  Simon Armbruster

IPC: H01L29/84

CPC classification number: B81B3/0086 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2203/0127 ,  G01L9/0042 ,  G01L9/0073

Abstract: A micromechanical component having a conductive substrate, a first conductive layer provided above the substrate and that forms, above a cavity provided in the substrate, an elastically deflectable diaphragm region of monocrystalline silicon and an adjacent peripheral region, a circuit trace level provided above the first conductive layer in a manner that is electrically insulated from the first conductive layer, the circuit trace level having above the diaphragm region a first electrode region and having above the peripheral region a first connection region electrically connected to the same, and a second conductive layer that is provided above the circuit trace level, the second conductive layer having above the diaphragm region a second electrode region that is electrically insulated from the first electrode region, and having above the peripheral region a second connection region electrically insulated from the second electrode region and electrically connected to the first connection region. Also provided is a suitable production method.

Abstract translation: 一种具有导电衬底的微机械部件，设置在衬底上方并在衬底中设置的空腔之上形成的第一导电层，单晶硅和相邻外围区域的可弹性偏转的膜片区域，设置在第一 导电层，其与第一导电层电绝缘的方式，电路迹线电平在隔膜区域上方具有第一电极区域，并且在周边区域上方具有与其电连接的第一连接区域;以及第二导电层， 设置在所述电路迹线电平之上，所述第二导电层在所述光阑区域上方具有与所述第一电极区域电绝缘的第二电极区域，并且在所述外围区域上方具有与所述第二电极区域电绝缘的第二连接区域， 连接到第一个连接 离子区。 还提供了合适的生产方法。

公开(公告)号：US08298962B2

公开(公告)日：2012-10-30

申请号：US12892008

申请日：2010-09-28

Applicant: Arnd Kaelberer ,  Helmut Baumann ,  Roland Scheuerer ,  Heribert Weber

Inventor： Arnd Kaelberer ,  Helmut Baumann ,  Roland Scheuerer ,  Heribert Weber

IPC: H01L21/302 ,  H01L21/461 ,  H01L23/58

CPC classification number: B81C1/00539 ,  B81C1/00619 ,  B81C1/00626 ,  H01L21/30608

Abstract: A device made of single-crystal silicon having a first side, a second side which is situated opposite to the first side, and a third side which extends from the first side to the second side, the first side and the second side each extending in a 100 plane of the single-crystal silicon, the third side extending in a first area in a 111 plane of the single-crystal silicon. The third side extends in a second area in a 110 plane of the single-crystal silicon. Furthermore, a production method for producing a device made of single-crystal silicon is described.

Abstract translation: 由单晶硅制成的器件，其具有第一侧，与第一侧相对的第二侧，以及从第一侧延伸到第二侧的第三侧，第一侧和第二侧各自延伸 单晶硅的100平面，第三面在单晶硅的111平面的第一区域中延伸。 第三面在单晶硅的110平面的第二区域中延伸。 此外，描述了用于制造由单晶硅制成的器件的制造方法。

公开(公告)号：US20120248552A1

公开(公告)日：2012-10-04

申请号：US13431399

申请日：2012-03-27

Applicant: Hubert BENZEL ,  Heribert Weber

Inventor： Hubert BENZEL ,  Heribert Weber

IPC: H01L21/02 ,  H01L29/84

CPC classification number: G01L9/0042 ,  G01L9/0045 ,  G01L9/0054 ,  G01P15/0802 ,  G01P15/123 ,  G01P2015/084

Abstract: An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.

Abstract translation: 提供了用于压电电阻器和半导体材料的电绝缘护套，使得压敏电阻器能够在高温范围内使用，例如用于在高于200℃的较高环境温度下测量。掺杂电阻区域最初由 至少一个周向基本上垂直的沟槽，并且通过在整个区域上的蚀刻而被切削。 然后在沟槽的壁和底切区域上形成电绝缘层，使得电阻区域通过电绝缘层与相邻的半导体材料电绝缘。

公开(公告)号：US20120049301A1

公开(公告)日：2012-03-01

申请号：US13291350

申请日：2011-11-08

Applicant: Roland Scheuerer ,  Heribert Weber ,  Eckhard Graf

Inventor： Roland Scheuerer ,  Heribert Weber ,  Eckhard Graf

IPC: H01L29/84

CPC classification number: B81C1/00095 ,  H01L21/76898 ,  H01L23/481

Abstract: A method for manufacturing a micromechanical component is proposed. In this context, at least one trench structure having a depth less than the substrate thickness is to be produced in a substrate. In addition, an insulating layer and a filler layer are produced or applied on a first side of the substrate. The filler layer comprises a filler material that substantially fills up the trench structure. A planar first side of the substrate is produced by way of a subsequent planarization within a plane of the filler layer or of the insulating layer or of the substrate. A further planarization of the second side of the substrate is then accomplished. A micromechanical component that is manufactured in accordance with the method is also described.

Abstract translation: 提出了一种制造微机械部件的方法。 在本上下文中，在衬底中产生具有小于衬底厚度的深度的至少一个沟槽结构。 此外，在基板的第一面上制造或施加绝缘层和填充层。 填充层包括基本上填充沟槽结构的填充材料。 衬底的平面第一侧通过在填充层或绝缘层或衬底的平面内的随后的平坦化产生。 然后完成衬底的第二侧的进一步的平坦化。 还描述了根据该方法制造的微机械部件。

公开(公告)号：US08123963B2

公开(公告)日：2012-02-28

申请号：US12152241

申请日：2008-05-12

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

IPC: H01L21/302 ,  B81C1/00

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00595 ,  B81C2201/0115 ,  G01L9/0045 ,  H01L21/3063

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

Abstract translation: 一种制造半导体部件的方法包括在所述半导体部件的p掺杂层中形成n掺杂层，其中所述n掺杂层包括以下中的至少一种：筛状层或网状层。 该方法还包括在n掺杂层的材料之间对p-掺杂层进行腐蚀蚀刻以形成顶部电极，以及在n-掺杂层下方形成空腔。

公开(公告)号：US20120045628A1

公开(公告)日：2012-02-23

申请号：US13318435

申请日：2010-04-07

Applicant: Julian Gonska ,  Heribert Weber

Inventor： Julian Gonska ,  Heribert Weber

IPC: B32B3/00 ,  B23K35/34

CPC classification number: B81C1/00269 ,  B81B7/0029 ,  B81C2203/0118 ,  B81C2203/019 ,  B81C2203/035 ,  Y10T428/24802

Abstract: A method is described for producing a micromechanical component. The method includes providing a first substrate, providing a second substrate, developing a projecting patterned element on the second substrate, and connecting the first and the second substrate via the projecting patterned element. The method provides that the connecting of the first and the second substrate includes eutectic bonding. Also described is a micromechanical component, in which a first and a second substrate are connected to each other.

Abstract translation: 描述了用于制造微机械部件的方法。 该方法包括提供第一衬底，提供第二衬底，在第二衬底上显影突出的图案化元件，以及经由突出图案化元件连接第一和第二衬底。 该方法提供了第一和第二基板的连接包括共晶接合。 还描述了一种微机械部件，其中第一和第二基板彼此连接。

公开(公告)号：US20100258884A1

公开(公告)日：2010-10-14

申请号：US12798868

申请日：2010-04-12

Applicant: Julian Gonska ,  Axel Grosse ,  Heribert Weber ,  Ralf Hausner

Inventor： Julian Gonska ,  Axel Grosse ,  Heribert Weber ,  Ralf Hausner

IPC: H01L29/84 ,  H01L21/02

CPC classification number: B81C3/001 ,  B81C2203/019

Abstract: A method for attaching a first carrier device to a second carrier device includes forming at least one first bond layer and/or solder layer on a first exterior of the first carrier device, a partial surface being framed by the at least one first bond layer and/or solder layer, and placing the first carrier device on the second carrier device and fixedly bonding or soldering the first carrier device to the second carrier device. The at least one first bond layer and/or solder layer includes a first cover area which is larger than a first contact area.

Abstract translation: 用于将第一载体装置附接到第二载体装置的方法包括在第一载体装置的第一外部上形成至少一个第一接合层和/或焊料层，部分表面由至少一个第一接合层和 /或焊料层，并且将第一载体装置放置在第二载体装置上，并将第一载体装置固定地接合或焊接到第二载体装置。 所述至少一个第一接合层和/或焊料层包括大于第一接触区域的第一覆盖区域。

公开(公告)号：US07479234B2

公开(公告)日：2009-01-20

申请号：US10492009

申请日：2002-09-04

Applicant: Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

IPC: H01B13/00

CPC classification number: B81C1/00047 ,  B81C1/00246 ,  B81C2201/0115 ,  B81C2201/014

Abstract: A method is proposed which will enable cavities having optically transparent walls to be produced simply and cost-effectively in a component by using standard methods of microsystems technology. For this purpose, a silicon region is first produced, which is surrounded on all sides by at least one optically transparent cladding layer. At least one opening is then produced in the cladding layer. Over this opening, the silicon surrounded by the cladding layer is dissolved out, forming a cavity within the cladding layer. In this context, the cladding layer acts as an etch barrier layer.

Abstract translation: 提出了一种通过使用微系统技术的标准方法，能够简单且成本有效地在部件中产生具有光学透明壁的空腔的方法。 为此目的，首先制造出硅区域，其通过至少一个光学透明覆层在所有侧面上被包围。 然后在包层中产生至少一个开口。 在该开口上，由包覆层包围的硅被溶出，在包覆层内形成空腔。 在本文中，包覆层用作蚀刻阻挡层。