公开(公告)号：US5899709A

公开(公告)日：1999-05-04

申请号：US627083

申请日：1996-04-03

申请人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

IPC分类号： H01L21/321 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/49 ,  H01L21/28 ,  H01L21/283

CPC分类号： H01L27/1214 ,  H01L21/32105 ,  H01L29/4908 ,  H01L29/66757 ,  H01L29/66765

摘要： An improved method for manufacturing an insulated gate field effect transistor is described. The method comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on said semiconductor film, forming a gate electrode on said gate insulating film with said gate insulating film inbetween, anoding said gate electrode in order to coat an external surface of said gate electrode with an oxide film thereof and applying a negative or positive voltage to said gate electrode with respect to said semiconductor film. Lattice defects and interfacial states caused by the application of a positive voltage during the anoding are effectively eliminated by the negative voltage application.

摘要翻译： 描述了用于制造绝缘栅场效应晶体管的改进方法。 该方法包括以下步骤：在绝缘基板上形成半导体膜，在所述半导体膜上形成栅极绝缘膜，在所述栅极绝缘膜上形成栅电极，在其间具有栅极绝缘膜，对所述栅极电极进行涂覆 所述栅电极的外表面具有氧化膜，并相对于所述半导体膜向所述栅电极施加负电压或正电压。 通过施加负电压，能够有效地消除由于在安装期间施加正电压引起的晶格缺陷和界面状态。

公开(公告)号：US5545571A

公开(公告)日：1996-08-13

申请号：US43782

申请日：1993-04-06

申请人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Hongyong Zhang ,  Hideki Uochi ,  Hiroki Adachi ,  Yasuhiko Takemura

IPC分类号： H01L21/321 ,  H01L21/336 ,  H01L21/84 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/66757 ,  H01L21/32105 ,  H01L21/84 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78666

摘要： An improved method for manufacturing an insulated gate field effect transistor is described. The method comprises the steps of forming a semiconductor film on an insulating substrate, forming a gate insulating film on said semiconductor film, forming a gate electrode on said gate insulating film with said gate insulating film inbetween, anoding said gate electrode in order to coat an external surface of said gate electrode with an oxide film thereof and applying a negative or positive voltage to said gate electrode with respect to said semiconductor film. Lattice defects and interfacial states caused by the application of a positive voltage during the anoding are effectively eliminated by the negative voltage application.

摘要翻译： 描述了用于制造绝缘栅场效应晶体管的改进方法。 该方法包括以下步骤：在绝缘基板上形成半导体膜，在所述半导体膜上形成栅极绝缘膜，在所述栅极绝缘膜上形成栅电极，在其间具有栅极绝缘膜，对所述栅极电极进行涂覆 所述栅电极的外表面具有氧化膜，并相对于所述半导体膜向所述栅电极施加负电压或正电压。 通过施加负电压，能够有效地消除由于在安装期间施加正电压引起的晶格缺陷和界面状态。

公开(公告)号：US09573813B2

公开(公告)日：2017-02-21

申请号：US13551682

申请日：2012-07-18

申请人： Hiroatsu Todoriki ,  Yasuhiko Takemura ,  Kuniharu Nomoto

发明人： Hiroatsu Todoriki ,  Yasuhiko Takemura ,  Kuniharu Nomoto

IPC分类号： C01B31/00 ,  B01D61/44 ,  B01D61/46 ,  C01B31/04 ,  B82Y30/00 ,  B82Y40/00 ,  H01M4/583 ,  H01M4/62

CPC分类号： C01B31/043 ,  B01D61/44 ,  B01D61/445 ,  B01D61/46 ,  B01D2311/04 ,  B01D2311/18 ,  B82Y30/00 ,  B82Y40/00 ,  C01B31/0476 ,  C01B32/192 ,  C01B32/23 ,  H01M4/583 ,  H01M4/621 ,  H01M4/625

摘要： Highly-pure graphite oxide, graphene oxide, or graphene is mass-produced. Graphite is oxidized by an oxidizer, so that a graphite oxide solution is obtained, and electrodialysis is performed on the graphite oxide solution to remove aqueous ions, whereby the purity of graphite oxide is increased. Graphene oxide manufactured using the graphite oxide is mixed with powder, and the mixture is reduced, whereby graphene exhibiting conductive properties is yielded and the powder can be bonded. Such graphene can be used instead of a conduction auxiliary agent or a binder of a variety of batteries.

摘要翻译： 大量生产高纯石墨氧化物，氧化石墨烯或石墨烯。 石墨由氧化剂氧化，得到氧化石墨溶液，对氧化石墨溶液进行电渗析，除去水分离子，提高石墨氧化物的纯度。 使用石墨氧化物制造的石墨烯氧化物与粉末混合，并且将混合物还原，从而产生具有导电性能的石墨烯，并且可以结合粉末。 可以使用这样的石墨烯代替各种电池的导电助剂或粘合剂。

公开(公告)号：US09431400B2

公开(公告)日：2016-08-30

申请号：US13359529

申请日：2012-01-27

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L27/108 ,  H01L29/786 ,  G11C11/405 ,  H01L21/84 ,  H01L27/12 ,  H01L21/44 ,  H01L29/12 ,  H01L27/02

CPC分类号： H01L27/108 ,  G11C11/405 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1203 ,  H01L27/1207

摘要： A highly integrated DRAM is provided. A bit line is formed over a first insulator, a second insulator is formed over the bit line, third insulators which are in a stripe shape and the like are formed over the second insulator, and a semiconductor region and a gate insulator are formed to cover one of the third insulators. The bit line is connected to the semiconductor region through first contact plugs. Then, a conductive film is formed and subjected to anisotropic etching to form word lines at side surfaces of the third insulators, and a second contact plug is formed to be connected to a capacitor at a top of the one of the third insulators. By synchronizing the word lines, electric charge is accumulated or released through the capacitor. With such a structure, the area of a memory cell can be 4F2.

摘要翻译： 提供高度集成的DRAM。 在第一绝缘体上形成位线，在位线上形成第二绝缘体，在第二绝缘体上形成条形等的第三绝缘体，形成半导体区域和栅极绝缘体以覆盖 第三绝缘子之一。 位线通过第一接触插塞连接到半导体区域。 然后，形成导电膜并进行各向异性蚀刻以在第三绝缘体的侧表面处形成字线，并且形成第二接触插塞以连接到第三绝缘体之一的顶部的电容器。 通过使字线同步，通过电容器蓄积或释放电荷。 利用这种结构，存储单元的面积可以是4F2。

公开(公告)号：US09001564B2

公开(公告)日：2015-04-07

申请号：US13532117

申请日：2012-06-25

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G11C11/24 ,  G11C11/401 ,  H01L27/115 ,  G11C11/403 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  G11C16/04

CPC分类号： H01L27/1156 ,  G11C11/403 ,  G11C16/0433 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： It is an object to reduce power consumption of a 2Tr1C type semiconductor memory device. The absolute value of the threshold voltage of a reading transistor is made larger than a fluctuation range of a data potential of a bit line (or the fluctuation range of the data potential of the bit line is made smaller than the absolute value of the threshold voltage of the reading transistor), whereby the potential of a source line can be fixed, a fluctuation in a potential of a writing word line can be made smaller, and a potential of a reading word line is fluctuated only at the time of reading. Further, a gate of such a transistor the absolute value of the threshold voltage of which is large is formed using a material having a high work function, such as indium nitride.

摘要翻译： 本发明的目的是降低2Tr1C型半导体存储器件的功耗。 使读取晶体管的阈值电压的绝对值大于位线的数据电位的波动范围（或位线的数据电位的波动范围小于阈值电压的绝对值 的读取晶体管），由此可以固定源极线的电位，可以使写入字线的电位的波动变小，并且读取字线的电位仅在读取时波动。 此外，使用具有高功函数的材料，例如氮化铟，形成这种晶体管的阈值电压大的绝对值的栅极。

公开(公告)号：US08982607B2

公开(公告)日：2015-03-17

申请号：US13608512

申请日：2012-09-10

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G11C11/24 ,  G11C11/413 ,  G11C11/40 ,  G11C11/412

CPC分类号： G11C11/413 ,  G11C11/24 ,  G11C11/40 ,  G11C11/4125

摘要： In a memory element including a pair of inverters, a capacitor which holds data, and a switching element which controls accumulating and releasing of electric charge of the capacitor are provided. For example, one electrode of the capacitor is connected to a first node, which is an input or output terminal of one of the pair of inverters, and the other electrode of the capacitor is connected to one electrode the switching element. The other electrode of the switching element is connected to a second node, which is the output or input terminal of the one of the pair of inverters. With such a connection structure, the absolute value of the potential difference between the first node and the second node at the time of data restoring can be large enough, whereby errors at the time of data restoring can be reduced.

摘要翻译： 在包括一对反相器，保持数据的电容器和控制电容器的电荷的累积和释放的开关元件的存储元件中， 例如，电容器的一个电极连接到第一节点，第一节点是一对逆变器之一的输入或输出端子，电容器的另一个电极连接到开关元件的一个电极。 开关元件的另一个电极连接到作为该对逆变器中的一个的输出端或输入端的第二节点。 利用这样的连接结构，数据恢复时的第一节点与第二节点之间的电位差的绝对值可以足够大，从而可以减少数据恢复时的错误。

公开(公告)号：US08513773B2

公开(公告)日：2013-08-20

申请号：US13346172

申请日：2012-01-09

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10885 ,  H01L27/11551 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1207

摘要： A capacitor that has an electrode of an n-type semiconductor that is provided in contact with one surface of a dielectric, has a work function of 5.0 eV or higher, preferably 5.5 eV or higher, and includes nitrogen and at least one of indium, tin, and zinc. Since the electrode has a high work function, the dielectric can have a high potential barrier, and thus even when the dielectric is as thin as 10 nm or less, a sufficient insulating property can be maintained. In particular, a striking effect can be obtained when the dielectric is formed of a high-k material.

摘要翻译： 具有与电介质的一个表面接触的n型半导体的电极的电容器的功函数为5.0eV以上，优选为5.5eV以上，并且包括氮和铟， 锡和锌。 由于电极具有高的功函数，所以电介质可以具有高的势垒，因此即使当电介质薄到10nm以下时，也能够维持足够的绝缘性。 特别地，当电介质由高k材料形成时，可以获得显着的效果。

公开(公告)号：US20130003441A1

公开(公告)日：2013-01-03

申请号：US13532117

申请日：2012-06-25

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G11C11/24

CPC分类号： H01L27/1156 ,  G11C11/403 ,  G11C16/0433 ,  H01L21/82345 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545

摘要： It is an object to reduce power consumption of a 2Tr1C type semiconductor memory device. The absolute value of the threshold voltage of a reading transistor is made larger than a fluctuation range of a data potential of a bit line (or the fluctuation range of the data potential of the bit line is made smaller than the absolute value of the threshold voltage of the reading transistor), whereby the potential of a source line can be fixed, a fluctuation in a potential of a writing word line can be made smaller, and a potential of a reading word line is fluctuated only at the time of reading. Further, a gate of such a transistor the absolute value of the threshold voltage of which is large is formed using a material having a high work function, such as indium nitride.

摘要翻译： 本发明的目的是降低2Tr1C型半导体存储器件的功耗。 使读取晶体管的阈值电压的绝对值大于位线的数据电位的波动范围（或位线的数据电位的波动范围小于阈值电压的绝对值 的读取晶体管），由此可以固定源极线的电位，可以使写入字线的电位的波动变小，并且读取字线的电位仅在读取时波动。 此外，使用具有高功函数的材料，例如氮化铟，形成这种晶体管的阈值电压大的绝对值的栅极。

公开(公告)号：US08339562B2

公开(公告)日：2012-12-25

申请号：US12582762

申请日：2009-10-21

申请人： Shunpei Yamazaki ,  Yasuhiko Takemura

发明人： Shunpei Yamazaki ,  Yasuhiko Takemura

IPC分类号： G02F1/1345 ,  G02F1/1368

CPC分类号： H01L29/4908 ,  H01L27/1255 ,  H01L29/42384 ,  H01L2224/48091 ,  H01L2224/48464 ,  H01L2224/73204 ,  H01L2924/00014

摘要： Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display (LCD) on one substrate.

公开(公告)号：US20120275213A1

公开(公告)日：2012-11-01

申请号：US13449456

申请日：2012-04-18

申请人： Yasuhiko Takemura

发明人： Yasuhiko Takemura

IPC分类号： G11C11/24

CPC分类号： G11C11/404 ,  G11C11/4097 ,  H01L27/108 ,  H01L27/10814 ,  H01L27/10876 ,  H01L27/10894 ,  H01L28/91

摘要： In a semiconductor memory device, one electrode of a capacitor is connected to a bit line, and the other electrode of the capacitor is connected to a drain of a cell transistor. A source of the cell transistor is connected to a source line. When a stack capacitor, for example, is used in this structure, one electrode of the capacitor is used as part of the bit line. An impurity region formed on the semiconductor substrate or a wiring parallel to a word line can be used as the source line; thus, the structure of a DRAM is simplified.

摘要翻译： 在半导体存储器件中，电容器的一个电极连接到位线，电容器的另一个电极连接到单元晶体管的漏极。 单元晶体管的源极连接到源极线。 例如，当使用堆叠电容器时，电容器的一个电极用作位线的一部分。 可以使用形成在半导体衬底上的杂质区域或与字线平行的布线作为源极线; 因此，DRAM的结构被简化。