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    SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME
    21.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING THE SAME 有权
    半导体器件及其驱动方法

    公开(公告)号：US20120026787A1

    公开(公告)日：2012-02-02

    申请号：US13185840

    申请日：2011-07-19

    申请人： Hideki Uochi ,  Koichiro Kamata

    发明人： Hideki Uochi ,  Koichiro Kamata

    IPC分类号： G11C11/34 ,  H01L29/786

    CPC分类号： H01L29/7869 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/53 ,  G11C2213/76 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/788 ,  H01L29/792

    摘要： A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain.

    摘要翻译： 晶体管包括第一和第二控制栅极以及存储栅极。 存储栅极被制成具有特定电位的导体，然后制成绝缘体，从而保持电位。 通过使存储门成为导体，提供要存储的数据的潜力，并使存储门成为绝缘体来写入数据。 通过使存储栅极成为绝缘体来读取数据，向连接到晶体管的源极和漏极之一的读取信号线提供电位，向第一控制栅极提供读取数据的电位，然后检测电位 连接到另一个源极和漏极的位线。

    SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE
    22.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR DRIVING SEMICONDUCTOR DEVICE 有权
    用于驱动半导体器件的半导体器件和方法

    公开(公告)号：US20110286256A1

    公开(公告)日：2011-11-24

    申请号：US13108636

    申请日：2011-05-16

    申请人： Koichiro Kamata

    发明人： Koichiro Kamata

    IPC分类号： G11C5/06 ,  G11C7/00 ,  H01L27/105

    CPC分类号： G11C16/24 ,  G11C11/404 ,  G11C11/565 ,  G11C16/26 ,  H01L27/11521 ,  H01L27/1225 ,  H01L29/7869

    摘要： A semiconductor device with a reduced area and capable of higher integration and larger storage capacity is provided. A multi-valued memory cell including a reading transistor which includes a back gate electrode and a writing transistor is used. Data is written by turning on the writing transistor so that a potential according to the data is supplied to a node where one of a source electrode and a drain electrode of the writing transistor and a gate electrode of the reading transistor are electrically connected to each other, and then turning off the writing transistor and holding a predetermined potential in the node. Data is read by supplying a reading control potential to a control signal line connected to one of a source electrode and a drain electrode of the reading transistor, and then detecting potential change of a reading signal line.

    摘要翻译： 提供了具有减小面积并且能够更高集成度和更大存储容量的半导体器件。 使用包括包括背栅极和写入晶体管的读取晶体管的多值存储单元。 通过接通写入晶体管来写入数据，使得根据数据的电位被提供给写入晶体管的源电极和漏电极之一以及读取晶体管的栅极电极彼此电连接的节点 ，然后关闭写入晶体管并保持节点中的预定电位。 通过将读取控制电位提供给连接到读取晶体管的源电极和漏极之一的控制信号线，然后检测读取信号线的电位变化来读取数据。

    Wireless power feeding system and wireless power feeding method
    26.
    发明授权
    Wireless power feeding system and wireless power feeding method 有权
    无线供电系统和无线供电方式

    公开(公告)号：US08836170B2

    公开(公告)日：2014-09-16

    申请号：US13189816

    申请日：2011-07-25

    申请人： Yutaka Shionoiri ,  Koichiro Kamata ,  Misako Sato ,  Shuhei Maeda

    发明人： Yutaka Shionoiri ,  Koichiro Kamata ,  Misako Sato ,  Shuhei Maeda

    IPC分类号： H01F17/00 ,  H01F37/00 ,  H04B5/00 ,  H02J7/02

    CPC分类号： H02J50/12 ,  H02J7/025 ,  H02J50/20 ,  H02J50/40 ,  H02J50/80 ,  H02J50/90 ,  H04B5/0037 ,  H04B5/0093

    摘要： An object is to provide a power feeding system and a power feeding method which are more convenient for a power feeding user at the power receiving end. An object is to provide a power feeding system and a power feeding method which also allow a power feeding provider (a company) which feeds power (at the power transmitting end) to supply power without waste. A power feeding device which wirelessly supplies power to a power receiver detects the position and the resonant frequency of the power receiver to be supplied with power, and controls the frequency of a power signal to be transmitted to the power receiver on the basis of the information. An efficient power feeding service can be offered by transmitting a power signal to the power receiver at an optimum frequency for high power transmission efficiency.

    摘要翻译： 本发明的目的是提供一种供电系统和馈电方法，其对于电力接收端的馈电用户更为方便。 本发明的目的是提供一种馈电系统和馈电方法，其还允许馈电供应商（在发电端发电）供电而不浪费电力。 向功率接收器无线供电的供电装置检测供电电源的位置和谐振频率，并根据信息控制发送到电力接收器的电力信号的频率 。 通过以最佳频率向功率接收器发送功率信号以实现高功率传输效率，可以提供有效的馈电服务。

    Semiconductor device comprising protection circuit with oxide semiconductor
    27.
    发明授权
    Semiconductor device comprising protection circuit with oxide semiconductor 有权
    半导体装置包括具有氧化物半导体的保护电

    公开(公告)号：US08816469B2

    公开(公告)日：2014-08-26

    申请号：US13012160

    申请日：2011-01-24

    申请人： Koichiro Kamata

    发明人： Koichiro Kamata

    IPC分类号： H01L29/12

    CPC分类号： H02M1/32 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/07749 ,  H01L27/0248 ,  H01L27/0285 ,  H01L27/1225 ,  H02H9/046 ,  H02J7/025 ,  H02J17/00 ,  H02J50/12 ,  H02M7/217

    摘要： To prevent damage on an element even when a voltage high enough to break the element is input. A semiconductor device of the invention operates with a first voltage and includes a protection circuit which changes the value of the first voltage when the absolute value of the first voltage is higher than a reference value. The protection circuit includes: a control signal generation circuit generating a second voltage based on the first voltage and outputting the generated second voltage; and a voltage control circuit. The voltage control circuit includes a transistor which has a source, a drain, and a gate, and which is turned on or off depending on the second voltage input to the gate and thus controls whether the value of the first voltage is changed based on the amount of current flowing between the source and the drain. The transistor also includes an oxide semiconductor layer.

    摘要翻译： 即使输入足够高的电压来破坏元件，也能防止元件的损坏。 本发明的半导体器件以第一电压工作，并且包括当第一电压的绝对值高于参考值时改变第一电压的值的保护电路。 所述保护电路包括：控制信号生成电路，其基于所述第一电压生成第二电压，并输出所生成的第二电压; 和电压控制电路。 电压控制电路包括具有源极，漏极和栅极的晶体管，并且其根据输入到栅极的第二电压而导通或截止，从而基于第一电压的值是否改变第一电压的值 在源极和漏极之间流动的电流量。 晶体管还包括氧化物半导体层。

    Semiconductor memory cell having an oxide semiconductor transistor and erasable by ultraviolet light
    28.
    发明授权
    Semiconductor memory cell having an oxide semiconductor transistor and erasable by ultraviolet light 有权
    半导体存储单元具有氧化物半导体晶体管并可通过紫外光消除

    公开(公告)号：US08659941B2

    公开(公告)日：2014-02-25

    申请号：US12951899

    申请日：2010-11-22

    申请人： Koichiro Kamata ,  Yusuke Sekine

    发明人： Koichiro Kamata ,  Yusuke Sekine

    IPC分类号： G11C11/40

    CPC分类号： G11C16/0433 ,  G11C16/02 ,  G11C16/0483 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869

    摘要： A nonvolatile memory includes a memory cell including a first transistor and a second transistor. The first transistor includes a first channel, a first gate electrode, a first source electrode, and a first drain electrode. The second transistor includes a second channel made of oxide semiconductor material, a second gate electrode, a second source electrode, and a second drain electrode. One of the second source electrode and the second drain electrode is electrically connected to the first gate electrode. Data writing in the memory cell is done by raising the potential of a node between one of the second source electrode and the second drain electrode and the first gate electrode. Data erasure in the memory cell is done by irradiating the second channel with ultraviolet light and lowering the potential of the node.

    摘要翻译： 非易失性存储器包括具有第一晶体管和第二晶体管的存储单元。 第一晶体管包括第一沟道，第一栅极，第一源极和第一漏极。 第二晶体管包括由氧化物半导体材料制成的第二沟道，第二栅电极，第二源电极和第二漏电极。 第二源电极和第二漏电极中的一个电连接到第一栅电极。 通过提高第二源电极和第二漏电极之间的节点与第一栅电极之间的节点的电位来进行存储单元中的数据写入。 通过用紫外线照射第二通道并降低节点的电位来完成存储单元中的数据擦除。

    Semiconductor device and method for driving the same
    29.
    发明授权
    Semiconductor device and method for driving the same 有权
    半导体装置及其驱动方法

    公开(公告)号：US08432730B2

    公开(公告)日：2013-04-30

    申请号：US13185840

    申请日：2011-07-19

    申请人： Hideki Uochi ,  Koichiro Kamata

    发明人： Hideki Uochi ,  Koichiro Kamata

    IPC分类号： G11C11/34

    CPC分类号： H01L29/7869 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0069 ,  G11C2213/53 ,  G11C2213/76 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/788 ,  H01L29/792

    摘要： A transistor includes first and second control gates, and a storage gate. The storage gate is made to be a conductor, supplied with a specific potential, and then made to be an insulator, thereby holding the potential. Data is written by making the storage gate a conductor, supplying a potential of data to be stored, and making the storage gate an insulator. Data is read by making the storage gate an insulator, supplying a potential to a read signal line connected to one of a source and a drain of the transistor, supplying a potential for reading data to the first control gate, and then detecting a potential of a bit line connected to the other of the source and the drain.

    摘要翻译： 晶体管包括第一和第二控制栅极以及存储栅极。 存储栅极被制成具有特定电位的导体，然后制成绝缘体，从而保持电位。 通过使存储门成为导体，提供要存储的数据的潜力，并使存储门成为绝缘体来写入数据。 通过使存储栅极成为绝缘体来读取数据，向连接到晶体管的源极和漏极之一的读取信号线提供电位，向第一控制栅极提供读取数据的电位，然后检测电位 连接到另一个源极和漏极的位线。

    Driving method of a semiconductor device with an inverted period having a negative potential applied to a gate of an oxide semiconductor transistor
    30.
    发明授权
    Driving method of a semiconductor device with an inverted period having a negative potential applied to a gate of an oxide semiconductor transistor 有权
    具有施加到氧化物半导体晶体管的栅极的具有负电位的反相周期的半导体器件的驱动方法

    公开(公告)号：US08416622B2

    公开(公告)日：2013-04-09

    申请号：US13108252

    申请日：2011-05-16

    申请人： Koichiro Kamata

    发明人： Koichiro Kamata

    IPC分类号： G11C16/04

    CPC分类号： G11C11/4076 ,  G11C11/404 ,  G11C16/02

    摘要： A period (inverted period) in which a high negative potential is applied to a gate of the transistor is provided between a writing period and a retention period. In the inverted period, supply of positive electric charge from the drain of the transistor to the oxide semiconductor layer is promoted. Thus, accumulation of positive electric charge in the oxide semiconductor layer or at the interface between the oxide semiconductor layer and a gate insulating film can converge in a short time. Therefore, it is possible to suppress a decrease in the positive electric charge in the node electrically connected to the drain of the transistor in the retention period after the inverted period. That is, the temporal change of data stored in the semiconductor device can be suppressed.

    摘要翻译： 在写入期间和保持期间之间，设置向晶体管的栅极施加高负电位的期间（反转期间）。 在反相期间，促进了从晶体管的漏极到氧化物半导体层的正电荷的供给。 因此，在氧化物半导体层中或在氧化物半导体层和栅极绝缘膜之间的界面处的正电荷的积累可以在短时间内收敛。 因此，可以抑制在倒置时间段之后的保持期间电连接到晶体管的漏极的节点中的正电荷的减少。 也就是说，可以抑制存储在半导体器件中的数据的时间变化。