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公开(公告)号：US09190413B2
公开(公告)日：2015-11-17
申请号：US13019330
申请日：2011-02-02
IPC分类号： H01L27/105 , H01L27/115 , H01L27/12
CPC分类号： H01L27/108 , H01L27/105 , H01L27/1052 , H01L27/1156 , H01L27/1225
摘要： A semiconductor device with a novel structure in which stored data can be held even when power is not supplied and there is no limitation on the number of times of writing. In the semiconductor device, a plurality of memory cells each including a first transistor, a second transistor, and a capacitor is provided in matrix and a wiring (also called a bit line) for connecting one memory cell to another memory cell and a source or drain electrode of the first transistor are electrically connected to each other through a source or drain electrode of the second transistor. Accordingly, the number of wirings can be smaller than that in the case where the source or drain electrode of the first transistor and the source or drain electrode of the second transistor are connected to different wirings. Thus, the degree of integration of the semiconductor device can be increased.
摘要翻译： 具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且对写入次数没有限制。 在半导体装置中，以矩阵形式设置有各自包括第一晶体管，第二晶体管和电容器的多个存储单元，以及用于将一个存储单元连接到另一个存储单元的源（或称为位线） 第一晶体管的漏极电极通过第二晶体管的源极或漏极电极彼此电连接。 因此，布线数量可以比第一晶体管的源极或漏极以及第二晶体管的源极或漏极连接到不同的布线的情况下的布线数量小。 因此，可以提高半导体器件的集成度。
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公开(公告)号：US08649208B2
公开(公告)日：2014-02-11
申请号：US13473752
申请日：2012-05-17
CPC分类号： G11C11/404 , G11C16/0433 , H01L27/1156 , H01L27/1225 , H01L27/1255
摘要： A semiconductor device includes a nonvolatile memory cell including a writing transistor including an oxide semiconductor, a reading transistor including a semiconductor material different from that of the writing transistor, and a capacitor. Data is written to the memory cell by turning on the writing transistor so that a potential is supplied to a node where a source electrode of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor so that a predetermined potential is held in the node. Data is read out from the memory cell by supplying a precharge potential to a bit line, stopping the supply of the potential to the bit line, and determining whether the potential of the bit line is kept at the precharge potential or decreased.
摘要翻译： 半导体器件包括：非易失性存储单元，包括具有氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管，以及电容器。 通过接通写入晶体管将数据写入存储单元，使得电位被提供给写入晶体管的源电极，电容器的一个电极和读取晶体管的栅极电连接的节点，以及 然后关闭写入晶体管，使得在节点中保持预定的电位。 通过向位线提供预充电电位，停止对位线的电位供给，以及确定位线的电位是否保持在预充电电位还是减小，从存储单元读出数据。
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公开(公告)号：US08467232B2
公开(公告)日：2013-06-18
申请号：US13193966
申请日：2011-07-29
IPC分类号： G11C11/24
CPC分类号： G11C16/0408 , G11C11/405 , G11C11/4076 , G11C11/4087 , H01L27/11521 , H01L27/1156 , H01L27/1207
摘要： In a semiconductor device which includes a bit line, m (m is a natural number of 3 or more) word lines, a source line, m signal lines, first to m-th memory cells, and a driver circuit, the memory cell includes a first transistor and a second transistor for storing electrical charge accumulated in a capacitor, and the second transistor includes a channel formed in an oxide semiconductor layer. In the semiconductor device, the driver circuit generates a signal to be output to a (j−1)th (j is a natural number of 3 or more) signal line with the use of a signal to be output to a j-th signal line.
摘要翻译： 在包括位线的m（m为3以上的自然数）字线，源极线，m条信号线，第1〜第m存储器单元和驱动电路的半导体器件中，所述存储单元包括 第一晶体管和第二晶体管，用于存储积聚在电容器中的电荷，第二晶体管包括形成在氧化物半导体层中的沟道。 在半导体装置中，驱动电路使用要输出到第j信号的信号，生成输出到第（j-1）（j为3以上的自然数）信号线的信号 线。
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公开(公告)号：US08450783B2
公开(公告)日：2013-05-28
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/085
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
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公开(公告)号：US08422272B2
公开(公告)日：2013-04-16
申请号：US13195105
申请日：2011-08-01
IPC分类号： G11C11/24
CPC分类号： H01L27/1052 , G11C11/404 , G11C11/405 , G11C11/4091 , G11C16/0408 , G11C16/08 , G11C16/24 , H01L21/02565 , H01L21/02631 , H01L21/425 , H01L21/441 , H01L21/477 , H01L27/108 , H01L27/11521 , H01L27/11526 , H01L27/1156 , H01L27/1207 , H01L27/1222 , H01L27/1225 , H01L27/124 , H01L27/1255 , H01L29/66969 , H01L29/78651 , H01L29/7869 , H01L29/78696
摘要： A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
摘要翻译： 提供了包括非易失性存储单元的半导体器件，其中包括包括氧化物半导体的写入晶体管，包括与写入晶体管不同的半导体材料的读取晶体管和电容器。 通过接通写入晶体管并将电位施加到写入晶体管的源极（或电极），电容器的一个电极和读取晶体管的栅电极的节点处，将数据写入存储单元 电连接，然后关闭写入晶体管，使得预定量的电荷被保持在节点中。 此外，当使用p沟道晶体管作为读取晶体管时，读取电位为正电位。
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公开(公告)号：US08320162B2
公开(公告)日：2012-11-27
申请号：US13022407
申请日：2011-02-07
IPC分类号： G11C11/24
CPC分类号： G11C11/24 , G11C11/403 , G11C11/405 , H01L27/1052 , H01L27/11521 , H01L27/1225
摘要： An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.
摘要翻译： 目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。 半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。 因此，可以充分降低半导体器件的功耗。
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公开(公告)号：US20120012845A1
公开(公告)日：2012-01-19
申请号：US13182488
申请日：2011-07-14
IPC分类号： H01L27/108
CPC分类号： H01L27/11517 , G11C16/0433 , G11C16/26 , H01L27/1156 , H01L29/78
摘要： A semiconductor device with a novel structure is provided, which can hold stored data even when no power is supplied and which has no limitations on the number of writing operations. A semiconductor device is formed using a material which enables off-state current of a transistor to be reduced significantly; e.g., an oxide semiconductor material which is a wide-gap semiconductor. With use of a semiconductor material which enables off-state current of a transistor to be reduced significantly, the semiconductor device can hold data for a long period. In a semiconductor device with a memory cell array, parasitic capacitances generated in the nodes of the first to the m-th memory cells connected in series are substantially equal, whereby the semiconductor device can operate stably.
摘要翻译： 提供具有新颖结构的半导体器件，其即使在没有供电的情况下也可以保存存储的数据，并且对写入操作的数量没有限制。 使用能够显着降低晶体管的截止电流的材料形成半导体器件; 例如，作为宽间隙半导体的氧化物半导体材料。 通过使用能够显着降低晶体管的截止电流的半导体材料，半导体器件可以长期保存数据。 在具有存储单元阵列的半导体器件中，在串联连接的第一至第m存储器单元的节点中产生的寄生电容基本相等，由此半导体器件可以稳定地工作。
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公开(公告)号：US20110156028A1
公开(公告)日：2011-06-30
申请号：US12978805
申请日：2010-12-27
申请人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
发明人： Shunpei Yamazaki , Jun Koyama , Kiyoshi Kato , Shuhei Nagatsuka , Takanori Matsuzaki , Hiroki Inoue
IPC分类号： H01L27/108
CPC分类号： H01L29/7869 , G11C16/0425 , H01L27/105 , H01L27/108 , H01L27/10802 , H01L27/10805 , H01L27/11 , H01L27/115 , H01L27/11517 , H01L27/11551 , H01L27/1156 , H01L27/11563 , H01L27/11568 , H01L27/1225 , H01L28/40 , H01L29/78693 , H01L29/788 , H01L29/7881 , H01L29/792
摘要： The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
摘要翻译： 半导体器件包括源极线，位线，信号线，字线，在源极线和位线之间并联连接的存储器单元，通过开关电连接到源极线和位线的第一驱动器电路 元件，通过开关元件电连接到源极线的第二驱动器电路，电连接到信号线的第三驱动电路，以及电连接到字线的第四驱动电路。 存储单元包括第一晶体管，包括第一栅电极，第一源电极和第一漏电极，第二晶体管包括第二栅电极，第二源电极和第二漏极，以及电容器。 第二晶体管包括氧化物半导体材料。
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公开(公告)号：US09697878B2
公开(公告)日：2017-07-04
申请号：US13472789
申请日：2012-05-16
IPC分类号： G11C5/06 , G11C8/14 , G11C11/408 , G11C8/08
CPC分类号： G11C8/14 , G11C8/08 , G11C11/408 , G11C11/4087 , G11C2216/14
摘要： A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line and a sub word line so that the word line divider is constituted. The transistor can include an oxide semiconductor for a semiconductor layer in which a channel is formed. Such a word line divider whose circuit structure is simplified is used in the storage device.
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公开(公告)号：US09384809B2
公开(公告)日：2016-07-05
申请号：US13472789
申请日：2012-05-16
IPC分类号： G11C5/06 , G11C8/14 , G11C11/408
摘要： A word line divider which has a simplified circuit structure and can operate stably is provided. A storage device which has a simplified circuit structure and can operate stably is provided. A transistor whose leakage current is extremely low is connected in series with a portion between a word line and a sub word line so that the word line divider is constituted. The transistor can include an oxide semiconductor for a semiconductor layer in which a channel is formed. Such a word line divider whose circuit structure is simplified is used in the storage device.
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