利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

108 条记录 (耗时 0.031 秒)

    SEMICONDUCTOR DEVICE HAVING SEAL WIRING
    21.
    发明申请
    SEMICONDUCTOR DEVICE HAVING SEAL WIRING 有权
    具有密封接线的半导体器件

    公开(公告)号：US20120181670A1

    公开(公告)日：2012-07-19

    申请号：US13428992

    申请日：2012-03-23

    申请人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

    发明人： Koji TAKEMURA ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Koji Koike

    IPC分类号： H01L23/00

    CPC分类号： H01L23/585 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes: an interlayer insulating film formed on a substrate; a wiring formed in the interlayer insulating film in a chip region of the substrate; a seal ring formed in the interlayer insulating film in a periphery of the chip region and continuously surrounding the chip region; and a first protective film formed on the interlayer insulating film having the wiring and the seal ring formed therein. A first opening is formed in the first protective film in a region located outside the seal ring when viewed from the chip region, and the interlayer insulating film is exposed in the first opening.

    摘要翻译： 半导体器件包括：形成在衬底上的层间绝缘膜; 在衬底的芯片区域中的层间绝缘膜中形成的布线; 密封环，形成在所述芯片区域的周围的所述层间绝缘膜中，并且连续地围绕所述芯片区域; 以及形成在其上形成有布线和密封环的层间绝缘膜上的第一保护膜。 当从芯片区域观察时，在位于密封环外侧的区域中的第一保护膜中形成第一开口，并且层间绝缘膜在第一开口中露出。

    Semiconductor memory device
    23.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41879E1

    公开(公告)日：2010-10-26

    申请号：US12155392

    申请日：2008-06-03

    申请人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    发明人： Shunichi Iwanari ,  Masahiko Sakagami ,  Hiroshige Hirano ,  Tetsuji Nakakuma ,  Takashi Miki ,  Yasushi Gohou ,  Kunisato Yamaoka ,  Yasuo Murakuki

    IPC分类号： G11C16/06

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1063 ,  G11C2207/229

    摘要： Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.

    摘要翻译： 提供了与SRAM兼容的半导体存储器件，并且能够在保持数据可靠性的同时进行高速数据传输操作。 当外部芯片使能信号XCE执行下降转换时，对存储器核心6的访问开始。 同时，接收外部写入使能信号XWE和外部地址信号ADD，并且选择与存储器核心6中对应于所接收的外部地址信号ADD的存储单元1。 当从存储器单元1读出的数据或对存储器单元1的数据写入完成时，根据外部芯片使能信号XCE的上升转变或者上升沿的转换激活重写定时器7 用于对存储单元1执行数据重写的外部写使能信号XWE。

    Semiconductor device
    24.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07538433B2

    公开(公告)日：2009-05-26

    申请号：US11452957

    申请日：2006-06-15

    申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    IPC分类号： H01L23/52

    CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

    摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。

    Semiconductor device
    26.
    发明申请
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US20070001308A1

    公开(公告)日：2007-01-04

    申请号：US11452957

    申请日：2006-06-15

    申请人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    发明人： Koji Takemura ,  Hiroshige Hirano ,  Yutaka Itoh ,  Hikari Sano ,  Masao Takahashi ,  Koji Koike

    IPC分类号： H01L23/52 ,  H01L23/48

    CPC分类号： H01L23/585 ,  H01L21/76832 ,  H01L23/522 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes at least three or more wiring layers stacked in an interlayer insulating film on a semiconductor substrate, a seal ring provided at the outer periphery of a chip region of the semiconductor substrate and a chip strength reinforcement provided in part of the chip region near the seal ring. The chip strength reinforcement is made of a plurality of dummy wiring structures and each of the plurality of dummy wiring structures is formed to extend across and within two or more of the wiring layers including one or none of the bottommost wiring layer and the topmost wiring layer using a via portion.

    摘要翻译： 一种半导体器件包括在半导体衬底上的层间绝缘膜中堆叠的至少三个或更多个布线层，设置在半导体衬底的芯片区域的外周处的密封环和在芯片区域的一部分中提供的芯片强度增强 靠近密封圈。 芯片强度加强件由多个虚拟布线结构构成，并且多个虚设布线结构中的每一个形成为跨越两个或更多个布线层中的两个或更多个布线层，包括最下面的布线层和最上面的布线层 使用通孔部分。

    Semiconductor memory device
    27.
    发明申请
    Semiconductor memory device 失效
    半导体存储器件

    公开(公告)号：US20060285378A1

    公开(公告)日：2006-12-21

    申请号：US11356213

    申请日：2006-02-17

    申请人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

    发明人： Kunisato Yamaoka ,  Hiroshige Hirano ,  Masahiko Sakagami

    IPC分类号： G11C11/22

    CPC分类号： G11C11/22

    摘要： In order to omit a reset transistor between a storage node and a cell plate line of a memory cell, a cell plate line is fixed to a potential substantially equal to a ground potential and a bit line is driven with positive and negative voltages.

    摘要翻译： 为了省略存储单元的存储节点和单元板极线之间的复位晶体管，单元板线固定为基本上等于接地电位的电位，并且用正和负电压驱动位线。

    Semiconductor storage device
    28.
    发明授权
    Semiconductor storage device 有权
    半导体存储设备

    公开(公告)号：US07136313B2

    公开(公告)日：2006-11-14

    申请号：US11121939

    申请日：2005-05-05

    申请人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    发明人： Yasuo Murakuki ,  Hiroshige Hirano ,  Yasushi Gohou ,  Masahiko Sakagami ,  Kunisato Yamaoka ,  Shunichi Iwanari ,  Tetsuji Nakakuma ,  Takashi Miki

    IPC分类号： G11C7/00 ,  G11C8/00

    CPC分类号： G11C29/816 ,  G11C11/22 ,  G11C29/789 ,  G11C2029/4402

    摘要： To provide a semiconductor storage device which can adapt to assembly processes involving different treatment temperatures, can become unrewritable when rewriting of data by the user is prohibited, negates the necessity for developing different semiconductor storage devices, and lowers development cost.A semiconductor storage device is provided with, as areas for storing faulty address information indicating a faulty area and operation mode setting information about the semiconductor storage device, a first setting function storage area 103 formed from electrically-rewritable nonvolatile memory and a second setting function storage area 102 formed from once-rewritable nonvolatile memory. Transfer of faulty address information to a faulty address register 111 and transfer of operation mode setting information to an operation mode register 110 are selectively performed.

    摘要翻译： 为了提供可以适应涉及不同处理温度的装配过程的半导体存储装置，当用户重写数据被禁止时，可以变得不可改变，否定了开发不同的半导体存储装置的必要性，并且降低了开发成本。 半导体存储装置设置有用于存储指示故障区域的有缺陷的地址信息和关于半导体存储装置的操作模式设置信息的区域，由可重写非易失性存储器和第二设置功能存储器形成的第一设置功能存储区域103 区域102由一次性可重写的非易失性存储器形成。 选择性地执行将故障地址信息传送到故障地址寄存器111和将操作模式设置信息传送到操作模式寄存器110。

    Voltage level conversion circuit
    29.
    发明申请
    Voltage level conversion circuit 有权
    电压电平转换电路

    公开(公告)号：US20050258886A1

    公开(公告)日：2005-11-24

    申请号：US11132272

    申请日：2005-05-19

    申请人： Hiroshige Hirano

    发明人： Hiroshige Hirano

    IPC分类号： H03K19/0185 ,  H03K3/012 ,  H03K3/356 ,  H03K17/10 ,  H03L5/00

    CPC分类号： H03K3/012 ,  H03K3/356113 ,  H03K3/356165 ,  H03K17/102

    摘要： A voltage level conversion circuit 101 is provided with a level converter 101a for converting a VDD1 system input signal into a VDD2 system signal, and a NOT circuit 30 for inverting the level-converted input signal and outputting the inverted signal, and the outputs of VDD1 system NOT circuits 21a and 21b constituting the level converter 101a are input to only high breakdown voltage transistors Qhn1 and Qhn2 in the level converter 101a while a signal having a logical voltage level corresponding to the low power supply voltage VDD2 is input to low breakdown voltage transistors Qlp1 and Qlp2, and further, only the input signal level-converted by the level converter 101a is input to the NOT circuit 30.

    摘要翻译： 电压电平转换电路101具有用于将VDD 1系统输入信号转换为VDD 2系统信号的电平转换器101a和用于反相电平转换输入信号并输出​​反相信号的NOT电路30， 构成电平转换器101a的VDD1系统NOT电路21a和21b的输出仅输入到电平转换器101a中的高击穿电压晶体管Qhn 1和Qhn 2，而具有对应于低功率的逻辑电压电平的信号 电源电压VDD 2被输入到低击穿电压晶体管Qlp1和Q1p2，此外，仅电平转换器101a的电平转换的输入信号被输入到NOT电路30。

    Ferroelectric memory device
    30.
    发明授权
    Ferroelectric memory device 失效
    铁电存储器件

    公开(公告)号：US06353550B1

    公开(公告)日：2002-03-05

    申请号：US09661370

    申请日：2000-09-13

    申请人： Hiroshige Hirano

    发明人： Hiroshige Hirano

    IPC分类号： G11C1112

    CPC分类号： G11C11/22

    摘要： The ferroelectric memory device includes a plurality of memory cells arranged in a matrix at crossings of a plurality of word lines and a plurality of bit lines. Each memory cell includes at least one ferroelectric capacitor composed of a ferroelectric film and first and second electrodes sandwiching the ferroelectric film, a memory cell transistor interposed between the bit line and the first electrode of the ferroelectric capacitor, a cell plate line connected to the second electrode of the ferroelectric capacitor, a reset voltage supply line for supplying a voltage of a potential substantially identical to the potential at the cell plate line, a reset transistor interposed between the reset voltage supply line and the first electrode of the ferroelectric capacitor, and a reset control signal line for controlling ON/OFF of the reset transistor.

    摘要翻译： 铁电存储器件包括在多个字线和多个位线的交叉处以矩阵布置的多个存储单元。 每个存储单元包括至少一个由铁电体膜构成的铁电电容器和夹持铁电体膜的第一和第二电极，插入在位线和强电介质电容器的第一电极之间的存储单元晶体管，连接到第二 所述强电介质电容器的电极，用于提供与所述电池板线的电位基本相同的电位的电压的复位电压供给线，配置在所述复位电压供给线与所述强电介质电容的第一电极之间的复位晶体管， 用于控制复位晶体管的导通/截止的复位控制信号线。