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21.发明授权
公开(公告)号：US4819212A
公开(公告)日：1989-04-04
申请号：US50717
申请日：1987-05-18
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
摘要： A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.
摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，每个存储单元包括非易失性晶体管，多个行线，各行连接到布置在相应行上的存储器单元，多个列线连接到布置的存储单元 在对应的列上，地址缓冲电路，用于在其地址输入端接收外部地址信号，并响应于所接收的外部地址信号输出内部地址信号，连接到列线的列线选择晶体管，列解码电路 用于选择性地偏置列线选择晶体管，用于选择性地偏置行线的行解码电路，以及用于检测由列线选择晶体管选择的列线的电位的数据检测电路。 该装置还包括控制单元，其产生用于控制地址缓冲电路的控制信号，使得内部地址信号被设置为预定值，以将所有行线设置为未选择状态，从而设置列线 通过列线选择晶体管，以预定电位。
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公开(公告)号：US5055706A
公开(公告)日：1991-10-08
申请号：US311798
申请日：1989-02-17
IPC分类号： H01L21/8238 , G11C11/407 , G11C11/4076 , H01L27/092 , H01L27/10 , H03K5/00 , H03K5/1252 , H03K5/13 , H03K5/131 , H03K5/133 , H03K5/134 , H03K5/135
CPC分类号： H03K5/133 , H03K5/1252 , H03K2005/00195
摘要： A semiconductor integrated circuit including delay means for generating an output signal delayed by a predetermined time with respect to an input signal when a logic level of said input signal changes in a first direction. The delay means receives a control signal and generates an internal control signal which is delayed by a predetermined time with respect to the control signal when a logic level of the control signal changes in a first direction, including a capacitor for delaying the control signal and a resistor having one end and having the other end connected to the capacitor.
摘要翻译： 一种半导体集成电路，包括延迟装置，用于当所述输入信号的逻辑电平在第一方向上变化时，产生相对于输入信号延迟预定时间的输出信号。 当控制信号的逻辑电平在第一方向上变化时，延迟装置接收控制信号并产生相对于控制信号延迟预定时间的内部控制信号，包括用于延迟控制信号的电容器和 电阻器具有一端并且另一端连接到电容器。
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公开(公告)号：US5420822A
公开(公告)日：1995-05-30
申请号：US218629
申请日：1994-03-28
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly.
摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。
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24.发明授权Semiconductor integrated circuit device having an object circuit to which output voltages of the sub- and main booster circuits are applied 失效半导体集成电路装置具有对主电路施加副主电路和主升压电路的输出电压的目标电路
公开(公告)号：US4905314A
公开(公告)日：1990-02-27
申请号：US184580
申请日：1988-04-21
IPC分类号： G11C17/00 , G11C5/14 , G11C16/06 , G11C16/30 , H01L21/822 , H01L21/8234 , H01L21/8247 , H01L27/04 , H01L27/088 , H01L27/10 , H01L29/788 , H01L29/792 , H02M3/07 , H03K3/356 , H03K17/06
CPC分类号： G11C5/145 , G11C16/30 , H03K17/06 , H03K3/356008
摘要： A sub-booster circuit for further stepping up an output voltage of a main booster circuit includes a first MOS transistor having a drain connected to the output terminal of the main booster circuit, and a gate connected to an input terminal of an object circuit, a second MOS transistor having a drain and a gate connected to the source of the first MOS transistor and a source connected to the input terminal of the object circuit, and a MOS capacitor having a first electrode connected to a connection node between the first and second MOS transistors and a second electrode connected to receive a clock pulse signal. A threshold voltage of the second MOS transistor is set to be larger in its absolute value than a threshold voltage of the first MOS transistor and the MOS capacitor has substantially the same threshold voltage as that of the second MOS transistor.
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公开(公告)号：US4804929A
公开(公告)日：1989-02-14
申请号：US101667
申请日：1987-09-28
CPC分类号： H03K17/223
摘要： A control pulse generator according to the present invention includes a voltage generator for generating an output voltage proportional to a power supply voltage, an inverter for generating an inversion signal whose signal level is inverted when the output voltage from the voltage generator reaches a predetermined value, and a pulse signal generator for delaying a level inversion timing of the inversion signal by a predetermined delay time, and generating a control pulse having a width corresponding to the delay time. According to the control pulse generator with the above arrangement, the width of the control pulse can be determined on the basis of the delay time of the pulse signal generator, regardless of rise states of the power supply voltage. In addition, the height of the control pulse can be set at a desired value according to a supply voltage to the pulse signal generator, regardless of rise states of the supply voltage.
摘要翻译： 根据本发明的控制脉冲发生器包括用于产生与电源电压成比例的输出电压的电压发生器，用于产生当来自电压发生器的输出电压达到预定值时信号电平反转的反相信号的反相器， 以及脉冲信号发生器，用于将反转信号的电平反转定时延迟预定的延迟时间，并产生具有对应于延迟时间的宽度的控制脉冲。 根据具有上述配置的控制脉冲发生器，无论电源电压的上升状态如何，可以基于脉冲信号发生器的延迟时间来确定控制脉冲的宽度。 此外，无论电源电压的上升状态如何，控制脉冲的高度可以根据与脉冲信号发生器的电源电压设定在期望值。
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26.发明授权
公开(公告)号：US4794562A
公开(公告)日：1988-12-27
申请号：US94458
申请日：1987-09-09
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： H01L29/7883 , H01L27/115
摘要： In an electrically-erasable/programmable nonvolatile semiconductor memory device according to the invention, a one-bit memory cell is constituted by a series circuit of a selecting MOS transistor and a data storage MOS transistor. A floating gate electrode and a control gate electrode are formed in the data storage MOS transistor, One portion of the floating gate electrode is formed on a channel region of the data storage MOS transistor through a gate insulating film. The other portion of the floating gate electrode is formed on a drain region of the data storage MOS transistor through a gate insulating film, a portion of which is sufficiently thinner than the gate insulating film. One and the other portions of the floating gate electrode are structurally separated from each other but are electrically connected with each other on a field region. A control gate electrode having substantially the same shape as that of the floating gate electrode is formed thereon through a gate insulating film.
摘要翻译： 在根据本发明的电可擦除/可编程非易失性半导体存储器件中，一位存储单元由选择MOS晶体管和数据存储MOS晶体管的串联电路构成。 在数据存储MOS晶体管中形成浮栅电极和控制栅极，通过栅极绝缘膜在浮动栅极的一部分形成在数据存储MOS晶体管的沟道区上。 浮置栅电极的另一部分通过栅极绝缘膜形成在数据存储MOS晶体管的漏极区上，栅极绝缘膜的一部分比栅极绝缘膜充分薄。 浮栅电极的一个和另外部分在结构上彼此分离，但是在场区域上彼此电连接。 通过栅极绝缘膜在其上形成具有与浮栅电极基本相同形状的控制栅电极。
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27.发明授权Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit 失效具有外部电容器的半导体存储器件，用于在EEPROM电路中为泵充电
公开(公告)号：US5519654A
公开(公告)日：1996-05-21
申请号：US450135
申请日：1995-05-25
申请人： Hideo Kato , Masamichi Asano , Shinji Saito , Shigeru Matsuda
发明人： Hideo Kato , Masamichi Asano , Shinji Saito , Shigeru Matsuda
摘要： A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V.sub.pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V.sub.CC) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.
摘要翻译： 一种具有存储单元阵列的半导体存储器件，所述存储单元阵列具有以能够电变化数据的矩阵形状的多个晶体管（存储单元MC）。 在向多个存储单元（MC）写入数据时，从多个写入电路（7）向多个存储单元（MC）施加写入电压（Vpp'）。 通过由电荷泵电路（21）升压内部电压（VCC）来产生写入电压。 在编写数据时，使用以下方法之一。 多个写入电路（7）以延迟定时的间隔由写入控制电路（20）依次启动。 每个存储单元（晶体管）（MC）的工作点由工作点控制装置控制，以减少电流。 电容器连接到电荷泵电路的输出侧，并且经由电容器将升压的写入电压提供给写入电路。
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公开(公告)号：US5732022A
公开(公告)日：1998-03-24
申请号：US812765
申请日：1997-03-06
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
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公开(公告)号：US5576994A
公开(公告)日：1996-11-19
申请号：US428060
申请日：1995-04-25
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。 此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问， 与常规装置相比。
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公开(公告)号：US5625591A
公开(公告)日：1997-04-29
申请号：US445960
申请日：1995-05-22
CPC分类号： G11C16/345 , G11C16/16 , G11C16/28 , G11C16/344 , G11C29/028 , G11C29/50 , G11C29/50004 , G11C29/50012 , G11C8/08 , G06F2201/81 , G11C16/04 , G11C2029/5004
摘要： When an erase voltage is applied to the sources of data erasable and rewritable memory cells each having a floating gate, the erasure characteristics of the memory cells can be improved by controlling the rise time of the erase voltage or by increasing the erase voltage stepwise. In test mode, no row lines are selected by a row decoder and further the sources of the respective memory cells are set to ground level. Under these conditions, in case there exists an overerased memory cell, this cell is turned on due to depletion, so that it is possible to detect the presence of the overerased memory cell on the basis of change in potential of the column line connected to this turned on memory cell. A differential amplifier is used to detect the change in potential of the column line. In the test mode, the potential of the column lines is compared with a reference potential applied to a dummy column line, and a source bias generating circuit applies a test potential suitable for test to the respective sources of the cells, to shift the threshold level of the respective cells in a positive direction, for instance. By applying this test potential to the cells, it is possible to detect the pseudo-threshold level shifted in the positive direction; that is, to detect the overerased status of the memory cell more properly. Further, the erasure is effected until the threshold level of a memory cell of the highest erasure speed reaches a predetermined level, irrespective of the threshold distribution width of the memory cells, thus realizing a higher speed access to the device of narrower threshold distribution width, as compared with the conventional device.
摘要翻译： 当擦除电压施加到每个具有浮动栅极的数据可擦除和可重写存储单元的源时，可以通过控制擦除电压的上升时间或逐步增加擦除电压来提高存储器单元的擦除特性。 在测试模式下，行解码器不选择行行，并且进一步将各存储单元的源设置为地电平。 在这些条件下，在存在过度存储单元的情况下，该单元由于耗尽而导通，从而可以基于连接到该存储单元的列线的电位变化来检测过度存储存储单元的存在 打开内存单元。 差分放大器用于检测列线的电位变化。 在测试模式中，将列线的电位与施加到虚拟列线的参考电位进行比较，并且源偏置产生电路将适合于测试的测试电位施加到单元的各个源，以将阈值电平 例如，各个单元的正方向。 通过将该测试电位施加到单元，可以检测正向偏移的伪阈值电平; 也就是说，更正确地检测存储器单元的过渡状态。 此外，擦除是直到最高擦除速度的存储单元的阈值水平达到预定水平，而不管存储器单元的阈值分布宽度如何，从而实现对较窄阈值分布宽度的设备的更高速度访问， 与常规装置相比。
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