公开(公告)号：US08825978B2

公开(公告)日：2014-09-02

申请号：US13584393

申请日：2012-08-13

申请人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

发明人： Yu-Meng Chaung ,  Chun-Hsiung Hung ,  Kuen-Long Chang ,  Ken-Hui Chen ,  Nai-Ping Kuo

IPC分类号： G06F12/00 ,  G06F13/42 ,  G11C29/00

CPC分类号： G11C7/1072 ,  G11C7/1066 ,  G11C7/222 ,  G11C2207/104

摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.

摘要翻译： 存储装置包括主机装置和从装置。 主机设备存储验证数据。 从设备包括存储单元，控制单元和逻辑单元。 控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。 逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。 前导码数据和存储数据根据内部时钟信号发送。 主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

公开(公告)号：US20090225607A1

公开(公告)日：2009-09-10

申请号：US12421523

申请日：2009-04-09

申请人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

发明人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C29/02 ,  G11C8/08 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

摘要： Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a power source or the second terminal. In an embodiment, the reference voltage is selected for identifying a leakage condition associated with the first word line. In another embodiment, the first switch is configured to couple the first word line to the power source for a first predetermined period of time to allow charging of the first word line. In another embodiment, the first switch is configured to couple the first word line to the second terminal of the comparator for at least a second predetermined period of time.

摘要翻译： 本发明的一些实施例提供了一种存储器件，其包括具有第一字线的第一存储器阵列和具有耦合到参考电压的第一端子的比较器电路，以及耦合到选择性地将第一字线耦合到第一字线的第一开关的第二端子 电源或第二终端。 在一个实施例中，选择参考电压以识别与第一字线相关联的泄漏状况。 在另一个实施例中，第一开关被配置为将第一字线耦合到电源第一预定时间段以允许对第一字线充电。 在另一个实施例中，第一开关被配置为将第一字线耦合到比较器的第二端子至少第二预定时间段。

公开(公告)号：US07295471B2

公开(公告)日：2007-11-13

申请号：US11273120

申请日：2005-11-14

申请人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

发明人： Wen-Yi Hsieh ,  Nai-Ping Kuo ,  Chun-Hsiung Hung ,  Ken-Hui Chen

IPC分类号： G11C11/34

CPC分类号： G11C16/0475 ,  G11C16/28 ,  G11C16/3454 ,  G11C16/3459

摘要： A program verification method for a memory device having a virtual array including a plurality of memory cells determines if leakage current passes through one or more neighboring memory cells to the programmed memory cell. The programmed memory cell is verified based on a first threshold state if leakage current is determined to pass through one or more neighboring memory cells. The programmed memory cell is verified based on a second threshold state if the leakage current is not determined to pass through one or more neighboring memory cells.

摘要翻译： 具有包括多个存储单元的虚拟阵列的存储器件的程序验证方法确定漏电流是否通过一个或多个相邻的存储器单元到编程的存储器单元。 如果确定泄漏电流通过一个或多个相邻存储器单元，则基于第一阈值状态来验证编程存储器单元。 如果泄漏电流未被确定通过一个或多个相邻存储器单元，则基于第二阈值状态来验证编程存储器单元。

公开(公告)号：US20070014157A1

公开(公告)日：2007-01-18

申请号：US11181983

申请日：2005-07-15

申请人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

发明人： Chun-Hsiung Hung ,  Chuan-Ying Yu ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Ching-Chung Lin ,  Kuen-Long Chang

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/24

摘要： A memory cell array, such as an EEPROM flash memory array, includes a current limiting circuit that limits a sum of leakage currents from nonselected memory cells during operation of the array, such as during a programming operation.

摘要翻译： 诸如EEPROM闪速存储器阵列的存储单元阵列包括电流限制电路，例如在编程操作期间限制阵列操作期间来自非选择存储单元的漏电流之和。

公开(公告)号：US08977912B2

公开(公告)日：2015-03-10

申请号：US11745244

申请日：2007-05-07

申请人： Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Su-Chueh Lo

发明人： Chun-Hsiung Hung ,  Han-Sung Chen ,  Nai-Ping Kuo ,  Su-Chueh Lo

IPC分类号： G11C29/24 ,  G11C29/56 ,  G11C29/00 ,  G11C29/54

CPC分类号： G11C29/56 ,  G11C29/56008 ,  G11C29/88

摘要： Methods and apparatuses are disclosed in which a repair instruction, such as from a tester, causes an integrated circuit undergoing testing to substitute defective locations of a first set of memory cells in the integrated circuit with a second set of memory cells in the integrated circuit, despite the repair instruction omitting the defective locations of the first set of memory cells of the integrated circuit.

摘要翻译： 公开了一种方法和装置，其中诸如来自测试者的修复指令使得正在进行测试的集成电路用集成电路中的第二组存储器单元替换集成电路中的第一组存储器单元的缺陷位置， 尽管修复指令省略了集成电路的第一组存储单元的缺陷位置。

公开(公告)号：US08929139B2

公开(公告)日：2015-01-06

申请号：US13308301

申请日：2011-11-30

申请人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

发明人： Nai-Ping Kuo ,  Su-Chueh Lo ,  Kuen-Long Chang ,  Chun-Hsiung Hung ,  Chia-Feng Cheng ,  Ken-Hui Chen ,  Yu-Chen Wang

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14

CPC分类号： G11C16/3409 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/14

摘要： Techniques are described herein for detecting and recovering over-erased memory cells in a flash memory device. In one embodiment, a flash memory device is described including a memory array including a plurality of blocks of memory cells. The device also includes a controller to perform a leakage-suppression process. The leakage-suppression process includes determining that a given block of memory cells includes one or more over-erased memory cells. Upon the determination, the leakage-suppression process also includes performing a soft program operation to increase the threshold voltage of the over-erased memory cells in the given block.

摘要翻译： 本文描述了用于检测和恢复闪存设备中的过擦除存储器单元的技术。 在一个实施例中，描述了一种闪存器件，其包括包括多个存储器单元块的存储器阵列。 该装置还包括执行泄漏抑制处理的控制器。 泄漏抑制过程包括确定给定的存储单元块包括一个或多个过擦除存储器单元。 在确定时，泄漏抑制处理还包括执行软程序操作以增加给定块中的被擦除的存储器单元的阈值电压。

公开(公告)号：US20130214820A1

公开(公告)日：2013-08-22

申请号：US13845576

申请日：2013-03-18

申请人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

发明人： Chun-Hsiung Hung ,  Kuen-Long Chang ,  Nai-Ping Kuo ,  Ming-Chih Hsieh

IPC分类号： H03K3/00

CPC分类号： H03K3/00 ,  H03K19/0002 ,  H03K19/09425

摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

摘要翻译： 集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。 输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。 输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。 所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

公开(公告)号：US07835178B2

公开(公告)日：2010-11-16

申请号：US12421523

申请日：2009-04-09

申请人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

发明人： Han-Sung Chen ,  Su-Chueh Lo ,  Chun-Hsiung Hung ,  Nai-Ping Kuo ,  Ming-Chih Hsieh ,  Wen-Pin Tsai

IPC分类号： G11C16/04

CPC分类号： G11C29/02 ,  G11C8/08 ,  G11C29/025 ,  G11C2029/1202 ,  G11C2029/5006

摘要： Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a power source or the second terminal. In an embodiment, the reference voltage is selected for identifying a leakage condition associated with the first word line. In another embodiment, the first switch is configured to couple the first word line to the power source for a first predetermined period of time to allow charging of the first word line. In another embodiment, the first switch is configured to couple the first word line to the second terminal of the comparator for at least a second predetermined period of time.

摘要翻译： 本发明的一些实施例提供了一种存储器件，其包括具有第一字线的第一存储器阵列和具有耦合到参考电压的第一端子的比较器电路，以及耦合到选择性地将第一字线耦合到第一字线的第一开关的第二端子 电源或第二终端。 在一个实施例中，选择参考电压以识别与第一字线相关联的泄漏状况。 在另一个实施例中，第一开关被配置为将第一字线耦合到电源第一预定时间段以允许对第一字线充电。 在另一个实施例中，第一开关被配置为将第一字线耦合到比较器的第二端子至少第二预定时间段。

公开(公告)号：US07180782B2

公开(公告)日：2007-02-20

申请号：US11151168

申请日：2005-06-10

申请人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

发明人： Chuan-Ying Yu ,  Nai-Ping Kuo ,  Ken-Hui Chen ,  Han-Sung Chen ,  Chun-Hsiung Hung

IPC分类号： G11C16/28

CPC分类号： G11C29/02 ,  G11C16/04 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5002

摘要： Non-volatile memory circuits according to the present invention provide a reference memory having multiple reference cells that are shared among a group of sense amplifiers through an interconnect conductor line. The higher number of reference cells for each reference memory generates a greater amount of electrical current for charging multiple source lines. The multiple source lines are coupled to the interconnect conductor bar for capacitance matching with a source line coupled to a memory cell in a main memory array. After a silicon wafer out, measurements to the capacitance produced by the source line in the main memory array and the capacitance produced by the source line in the reference array are taken for an optional trimming. A further calibration in capacitance matching is achieved by trimming one of the source lines that is coupled to the interconnect conductor bar and the reference memory, either by cutting a portion of the source line or adding a portion to the source line.

摘要翻译： 根据本发明的非易失性存储器电路提供具有通过互连导体线在一组读出放大器之间共享的多个参考单元的参考存储器。 每个参考存储器的较高数量的参考单元产生更大量的用于对多个源极线进行充电的电流。 多个源极线耦合到互连导体条，用于与耦合到主存储器阵列中的存储器单元的源极线的电容匹配。 在硅晶片出来之后，对由主存储器阵列中的源极线产生的电容的测量以及由参考阵列中的源极线产生的电容进行可选的修整。 电容匹配的另一校准是通过切割源极线的一部分或者将一部分添加到源极线来修剪耦合到互连导体条和参考存储器的源极线之一来实现的。

公开(公告)号：US20060267059A1

公开(公告)日：2006-11-30

申请号：US11137098

申请日：2005-05-25

申请人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Su-Chueh Lo ,  Nai-Ping Kuo ,  Ken-Hui Chen

发明人： Chuan-Ying Yu ,  Chun-Hsiung Hung ,  Su-Chueh Lo ,  Nai-Ping Kuo ,  Ken-Hui Chen

IPC分类号： H01L29/94

CPC分类号： H01L27/0207 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/11898

摘要： A wordline driver cell, coupled to at least one wordline, includes at least one diffusion region and at least one wordline driver semiconductor switching device formed in the at least one diffusion region. The at least one wordline driver semiconductor switching device has a channel width that is arranged perpendicular to a longitudinal axis of the at least one wordline.

摘要翻译： 耦合到至少一个字线的字线驱动器单元包括形成在至少一个扩散区域中的至少一个扩散区域和至少一个字线驱动器半导体开关器件。 所述至少一个字线驱动器半导体开关器件具有垂直于所述至少一个字线的纵向轴线布置的沟道宽度。