公开(公告)号：US20210028059A1

公开(公告)日：2021-01-28

申请号：US16934200

申请日：2020-07-21

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/768

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US20200168606A1

公开(公告)日：2020-05-28

申请号：US16696935

申请日：2019-11-26

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Steven Demuynck

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/308 ,  H01L29/66 ,  H01L29/786 ,  H01L21/02 ,  H01L29/423 ,  H01L29/06 ,  H01L29/417 ,  H01L21/3065

Abstract: The disclosed technology relates to a method of forming a stacked semiconductor device. One aspect includes fin structures formed by upper and lower channel layers which are separated by an intermediate layer. After preliminary fun cuts are formed in the fin structure, a sacrificial spacer is formed that covers end surfaces of an upper channel layer portion. Final fin cuts are formed in the fin structure where the lower channel layer is etched which defines a lower channel layer portion. Lower source/drain regions are formed on end surfaces of the lower channel layer portion. The sacrificial spacer shields the end surfaces of the upper channel layer portion allowing for selective deposition of material for the lower source/drain regions.

公开(公告)号：US20190271660A1

公开(公告)日：2019-09-05

申请号：US16292139

申请日：2019-03-04

Applicant: IMEC vzw

Inventor： Boon Teik Chan ,  Zheng Tao ,  Jean-Francois de Marneffe ,  Chang Chen

IPC: G01N27/414 ,  H01L29/66 ,  H01L21/306 ,  H01L21/308 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78 ,  G01N33/487 ,  C12Q1/6869

Abstract: The disclosed technology generally relates to a method of forming a nanoscale opening in a semiconductor structure, and more particularly to forming a nanoscale opening that can be used for sensing the presence of polymers, e.g., the individual bases of deoxyribonucleic acid (DNA) or ribonucleic acid (RNA). In one aspect, a method of forming a nanopore in a semiconductor fin includes providing a fin structure comprising a bottom layer and a top layer, pattering the top layer to form a pillar, and laterally embedding the pillar in a filler material. The method additionally includes forming an aperture in the filler material by removing the pillar, and forming the nanopore in the bottom layer by etching through the aperture. In another aspect, a semiconductor fin is fabricated using the method.

公开(公告)号：US20180166534A1

公开(公告)日：2018-06-14

申请号：US15822275

申请日：2017-11-27

Applicant: IMEC VZW

Inventor： Zheng Tao ,  Boon Teik Chan ,  Soon Aik Chew

IPC: H01L29/06 ,  H01L21/3065 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08 ,  H01L21/02

CPC classification number: H01L29/0673 ,  B82Y10/00 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/02282 ,  H01L21/02532 ,  H01L21/3065 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66 ,  H01L29/66439 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/775

Abstract: A method of forming a semiconductor device comprising horizontal nanowires is described. An example method involves providing a semiconductor structure comprising at least one fin, where the fin includes an alternating stack of layers of sacrificial material and nanowire material, and where the semiconductor structure includes a dummy gate partly covering the stack of layers. The method further involves at least partly removing the sacrificial material, in between the layers of nanowire material, next to the dummy gate thereby forming a void. Still further, the method involves providing spacer material within the void thereby forming an internal spacer. Yet still further the method involves removing the dummy gate, and selectively removing the sacrificial material in that part of the fin which was covered by the dummy gate, thereby releasing the nanowires. The internal spacer is provided before removing the dummy gate and the sacrificial material to release the nanowires.

公开(公告)号：US20170103889A1

公开(公告)日：2017-04-13

申请号：US15258838

申请日：2016-09-07

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Vasile Paraschiv ,  Efrain Altamirano Sanchez ,  Zheng Tao

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/3065 ,  H01L21/308

Abstract: A method for producing a pillar structure in a semiconductor layer, the method including providing a structure including, on a main surface, a semiconductor layer. A patterned hard mask layer stack is provided on the semiconductor layer that includes a first layer in contact with the semiconductor layer and a second layer overlying and in contact with the first layer. The semiconductor layer is etched using the patterned hard mask layer stack as a mask. The etching includes subjecting the structure to a first plasma thereby removing a first part of the semiconductor layer and at least a part of the second layer while preserving the first layer thereby, producing a first part of the pillar structure, thereafter; and subjecting the structure to a second plasma thereby removing a second part of the semiconductor layer thereby, producing a second part of the pillar structure.

公开(公告)号：US12237207B2

公开(公告)日：2025-02-25

申请号：US18469374

申请日：2023-09-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/74 ,  H01L21/8234 ,  H01L23/528 ,  H01L23/535

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US20240006228A1

公开(公告)日：2024-01-04

申请号：US18469374

申请日：2023-09-18

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Zheng Tao ,  Efrain Altamirano Sanchez ,  Anshul Gupta ,  Basoene Briggs

IPC: H01L21/74 ,  H01L21/8234 ,  H01L23/535 ,  H01L23/528

CPC classification number: H01L21/743 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/535 ,  H01L23/5286

Abstract: A method for forming a buried metal line in a semiconductor substrate comprises forming, at a position between a pair of semiconductor structures, a metal line trench in the semiconductor substrate at a level below a base of each semiconductor structure of the pair, and forming the metal line in the metal line trench by means of area selective deposition of a metal line material, followed by embedding the pair of semiconductor structures in an insulating layer.

公开(公告)号：US11862452B2

公开(公告)日：2024-01-02

申请号：US17006642

申请日：2020-08-28

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L21/762 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L21/02 ,  H01L29/775 ,  H01L21/822 ,  H01L29/10 ,  H01L21/768

CPC classification number: H01L21/76224 ,  H01L21/02175 ,  H01L21/76834 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1079 ,  H01L29/775

Abstract: In a first aspect, the present disclosure relates to a method for forming a contact isolation for a semiconductor device, comprising: providing a semiconductor structure comprising a trench exposing a contact thereunder, filling a bottom of the trench with a sacrificial material, infiltrating the sacrificial material with a ceramic material, and removing the sacrificial material.

公开(公告)号：US20220181197A1

公开(公告)日：2022-06-09

申请号：US17459384

申请日：2021-08-27

Applicant: IMEC VZW

Inventor： Zheng Tao

IPC: H01L21/74 ,  H01L23/535 ,  H01L23/522 ,  H01L21/84

Abstract: A method is provided for forming a semiconductor product including providing a substrate comprising a buried power rail; forming a sacrificial plug at a contact surface on the buried power rail; applying a front-end-of-line module for forming devices in the semiconductor substrate; providing a Via, through layers applied by the front-end-module, which joins the sacrificial plug on the buried power rail; selectively removing the sacrificial plug thereby obtaining a cavity above the buried power rail; filling the cavity with a metal to electrically connect the devices with the buried power rail, wherein the sacrificial plug is formed such that the contact surface area is larger than an area of a cross-section of the Via parallel with the contact surface.

公开(公告)号：US20210296500A1

公开(公告)日：2021-09-23

申请号：US17208800

申请日：2021-03-22

Applicant: IMEC VZW

Inventor： Boon Teik Chan ,  Waikin Li ,  Zheng Tao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06

Abstract: A method for partially filling a space between two superimposed structures in a semiconductor device under construction is provided. The method includes the steps of: (a) providing the two superimposed structures having said space therebetween; (b) entirely filling said space with a thermoplastic material; (c) removing a first portion of the thermoplastic material present in the space, the first portion comprising at least part of a top surface of the thermoplastic material, thereby leaving in said space a remaining thermoplastic material having a height; and (d) heating up the remaining photosensitive thermoplastic material so as to reduce its height. A replacement metal gate process for forming a different gate stack on two superimposed transistor channels in a semiconductor device under construction as well as a semiconductor device under construction is also provided.