公开(公告)号：US20230180400A1

公开(公告)日：2023-06-08

申请号：US18070849

申请日：2022-11-29

Applicant: Infineon Technologies AG

Inventor： Alexander Herbrandt ,  Philipp Bräutigam ,  Andre Arens ,  Marco Ludwig

IPC: H05K5/00 ,  H05K5/02

CPC classification number: H05K5/0026 ,  H05K5/0247 ,  H01L25/072

Abstract: An arrangement includes a housing and a printed circuit board (PCB) arranged vertically above the housing. The housing includes: at least one protrusion attached to sidewalls and arranged on an outside of the housing at a lower end with at least one first through hole provided in the protrusion; holding devices each arranged inside a first through hole and/or between the PCB and the first through hole; and fastening elements configured to attach the housing to a heat sink or base plate. Each holding device is configured to clamp a corresponding fastening element such that the fastening elements are secured in defined positions, and to align each fastening element with a different first through hole. The PCB includes second through holes each arranged vertically above and aligned with a different fastening element. A diameter of each second through hole is less than the largest diameter of the respective fastening element.

公开(公告)号：US20220065924A1

公开(公告)日：2022-03-03

申请号：US17009718

申请日：2020-09-01

Applicant: Infineon Technologies AG

Inventor： Jens Barrenscheen ,  Andre Arens

IPC: G01R31/28 ,  G01R31/40 ,  H03K17/18

Abstract: This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch. A driver circuit for the power switch may be configured to deliver a modulation signal to a control node of the power switch to control on/off switching of the power switch, wherein the driver circuit is further configured to modulate an output impedance of the driver circuit at the control node, perform one or more voltage measurements while modulating the output impedance of the driver circuit, and control the power switch based at least in part on the one or more voltage measurements.

公开(公告)号：US20180211917A1

公开(公告)日：2018-07-26

申请号：US15877749

申请日：2018-01-23

Applicant: Infineon Technologies AG

Inventor： Juergen Hoegerl ,  Andre Arens ,  Holger Torwesten

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/29 ,  H01L23/373 ,  H01L23/498 ,  H01L23/34 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/4853 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49541 ,  H01L23/49589 ,  H01L23/49861 ,  H01L23/50 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14251 ,  H01L2924/14252 ,  H01L2924/1426 ,  H01L2924/19105 ,  H01L2224/45099

Abstract: A semiconductor module is disclosed. In one example, the module includes a carrier, at least one semiconductor transistor disposed on the carrier, at least one semiconductor diode disposed on the carrier, at least one semiconductor driver chip disposed on the carrier, a plurality of external connectors, and an encapsulation layer covering the carrier, the semiconductor transistor, the semiconductor diode, and the semiconductor driver chip. The semiconductor transistor, the semiconductor diode, and the semiconductor driver chip are arranged laterally side by side on the carrier.

公开(公告)号：US20150092376A1

公开(公告)日：2015-04-02

申请号：US14499915

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Juergen Hoegerl ,  Magdalena Hoier

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00

CPC classification number: H05K1/111 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/181 ,  H05K3/28 ,  H05K3/284 ,  H05K7/1432 ,  H05K2201/0104 ,  H05K2201/042 ,  H05K2201/10303 ,  H05K2201/10318 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

Abstract translation: 印刷电路板（PCB）具有布置在其顶侧的第一结构化金属化和在垂直方向上布置在第一金属化下方的至少一个第二金属化，平行于第一金属化并与其绝缘。 在PCB顶侧也是裸露的半导体芯片，其具有通过接合线连接到PCB顶面上的第一金属化的相应接触焊盘的接触电极。 在操作期间，接触电极和对应的接触垫的第一部分承载高电压。 所有高电压接触焊盘通过电镀通孔导电连接到第二金属化。 绝缘层完全覆盖芯片周围的芯片和PCB的界定区域，并且所有高压承载接触焊盘和电镀通孔完全被绝缘层覆盖。 在操作期间，接触电极和对应的接触焊盘的第二部分处于低电压。

公开(公告)号：US20130285712A1

公开(公告)日：2013-10-31

申请号：US13871288

申请日：2013-04-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Peter Kanschat ,  Andre Arens ,  Hartmut Jasberg ,  Ulrich Michael Georg Schwarzer

IPC: H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163 ,  H03K17/168

Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.

Abstract translation: 一种用于驱动可控功率半导体开关的方法，具有第一输入端和耦合到电压源和负载的第一和第二输出端，提供功率半导体开关的输出的第一和第二输出端包括： 通过耦合到输入端的电压源装置，输出电流的关断边缘和功率半导体开关的输出电压。 输出电流和输出电压的接通边沿的梯度由耦合到输入端子的可控电流源装置调节并产生栅极驱动电流。 从输出电流的上升开始并以输出电压的降低结束的栅极驱动电流从一个开关操作到随后的开关操作的曲线最多在预定义的公差带内变化。