公开(公告)号：US20160126192A1

公开(公告)日：2016-05-05

申请号：US14529371

申请日：2014-10-31

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L25/00

Abstract: A power semiconductor module includes a direct copper bonded (DCB) substrate having a ceramic substrate, a first copper metallization bonded to a first main surface of the ceramic substrate and a second copper metallization bonded to a second main surface of the ceramic substrate opposite the first main surface. The power semiconductor module further includes a power semiconductor die attached the first copper metallization, a passive component attached the first copper metallization, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component. An integrated power module and a method of manufacturing the integrated power module are also provided.

Abstract translation: 功率半导体模块包括具有陶瓷衬底的直接铜键合（DCB）衬底，与陶瓷衬底的第一主表面接合的第一铜金属化层和与陶瓷衬底的第一主表面相对的陶瓷衬底的第二主表面接合的第二铜金属化 主表面。 功率半导体模块还包括附接第一铜金属化的功率半导体管芯，连接第一铜金属化的无源部件，封装功率半导体管芯和无源部件的第一隔离层，第一隔离层上的第一结构化金属化层， 以及从第一结构化金属化层延伸穿过第一隔离层到功率半导体管芯和无源部件的第一多个导电通孔。 还提供了集成电源模块和制造集成电源模块的方法。

公开(公告)号：US09924594B2

公开(公告)日：2018-03-20

申请号：US14499915

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Juergen Hoegerl ,  Magdalena Hoier

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00 ,  H05K1/18 ,  H05K1/02 ,  H05K3/28 ,  H05K7/14 ,  H05K1/14 ,  H01L23/31

CPC classification number: H05K1/111 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/181 ,  H05K3/28 ,  H05K3/284 ,  H05K7/1432 ,  H05K2201/0104 ,  H05K2201/042 ,  H05K2201/10303 ,  H05K2201/10318 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

公开(公告)号：US20150130071A1

公开(公告)日：2015-05-14

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L25/00 ,  H01L23/522

CPC classification number: H01L25/074 ,  H01L21/565 ,  H01L21/566 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/4334 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/5386 ,  H01L23/5389 ,  H01L25/162 ,  H01L25/165 ,  H01L25/50 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

Abstract translation: 半导体封装包括包括多个半导体晶体管芯片的第一半导体模块和设置在半导体晶体管芯片上方的第一封装层，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个半导体驱动器通道和设置在半导体驱动器通道上方的第二封装层。 半导体驱动器通道被配置为驱动半导体晶体管芯片。

公开(公告)号：US20190221521A1

公开(公告)日：2019-07-18

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/561 ,  H01L23/3135 ,  H01L23/3735 ,  H01L23/49811 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/00 ,  H01L24/25 ,  H01L25/00

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.

公开(公告)号：US09756726B2

公开(公告)日：2017-09-05

申请号：US14071296

申请日：2013-11-04

Applicant: Infineon Technologies AG

Inventor： Alexander Heinrich ,  Peter Scherl ,  Magdalena Hoier ,  Hans-Joerg Timme

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H05K1/14 ,  H01L23/00 ,  H05K3/36 ,  H05K3/32 ,  H05K3/40

CPC classification number: H05K1/11 ,  H01L24/45 ,  H01L24/46 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/45015 ,  H01L2224/45028 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45184 ,  H01L2224/4554 ,  H01L2224/48091 ,  H01L2224/48092 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48507 ,  H01L2224/48511 ,  H01L2224/85 ,  H01L2224/85181 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/111 ,  H05K1/14 ,  H05K3/32 ,  H05K3/36 ,  H05K3/4015 ,  H05K2201/04 ,  H05K2203/0285 ,  Y10T29/49126 ,  H01L2924/00 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/20756 ,  H01L2924/20757 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/00012 ,  H01L2224/48247 ,  H01L2224/43 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: An electronic device may comprise a semiconductor element and a wire bond connecting the semiconductor element to a substrate. Using a woven bonding wire may improve the mechanical and electrical properties of the wire bond. Furthermore, there may be a cost benefit. Woven bonding wires may be used in any electronic device, for example in power devices or integrated logic devices.

公开(公告)号：US10242969B2

公开(公告)日：2019-03-26

申请号：US14077696

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Angela Kessler ,  Magdalena Hoier

IPC: H01L25/07 ,  H01L23/31 ,  H01L23/522 ,  H01L25/00 ,  H01L21/56 ,  H01L23/373 ,  H01L23/433 ,  H01L23/538 ,  H01L23/498

Abstract: A semiconductor package includes a first semiconductor module including a plurality of semiconductor transistor chips and a first encapsulation layer disposed above the semiconductor transistor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of semiconductor driver channels and a second encapsulation layer disposed above the semiconductor driver channels. The semiconductor driver channels are configured to drive the semiconductor transistor chips.

公开(公告)号：US09780053B2

公开(公告)日：2017-10-03

申请号：US14941633

申请日：2015-11-15

Applicant: Infineon Technologies AG

Inventor： Magdalena Hoier ,  Peter Scherl ,  Manfred Schneegans

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/02

CPC classification number: H01L24/05 ,  H01L21/02697 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/02166 ,  H01L2224/03502 ,  H01L2224/03831 ,  H01L2224/04042 ,  H01L2224/05015 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/0518 ,  H01L2224/05557 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/0568 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4845 ,  H01L2224/48453 ,  H01L2224/48455 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/78301 ,  H01L2224/85205 ,  H01L2224/85365 ,  H01L2924/00014

Abstract: Various embodiments provide a method of forming a bondpad, wherein the method comprises providing a raw bondpad, and forming a recess structure at a contact surface of the raw bondpad, wherein the recess structure comprises sidewalls being inclined with respect to the contact surface.

公开(公告)号：US20150130048A1

公开(公告)日：2015-05-14

申请号：US14077694

申请日：2013-11-12

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L21/563 ,  H01L23/3107 ,  H01L23/3135 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072 ,  H01L25/18 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/1033 ,  H01L2924/1203 ,  H01L2924/12043 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00

Abstract: A semiconductor package includes a mold body having a first main face, a second main face opposite to the first main face and side faces connecting the first and second main faces, a first semiconductor module including a plurality of first semiconductor chips and a first encapsulation layer disposed above the first semiconductor chips, and a second semiconductor module disposed above the first semiconductor module. The second semiconductor module includes a plurality of second semiconductor channels and a second encapsulation layer disposed above the second semiconductor channels. The semiconductor package further includes a plurality of external connectors extending through one or more of the side faces of the mold body.

Abstract translation: 半导体封装包括具有第一主面，与第一主面相对的第二主面和连接第一主面和第二主面的侧面的模体，包括多个第一半导体芯片的第一半导体模块和第一封装层 设置在第一半导体芯片上方，以及设置在第一半导体模块上方的第二半导体模块。 第二半导体模块包括多个第二半导体沟道和设置在第二半导体沟道上方的第二封装层。 半导体封装还包括延伸穿过模具主体的一个或多个侧面的多个外部连接器。

公开(公告)号：US20150092376A1

公开(公告)日：2015-04-02

申请号：US14499915

申请日：2014-09-29

Applicant: Infineon Technologies AG

Inventor： Andre Arens ,  Juergen Hoegerl ,  Magdalena Hoier

IPC: H05K1/11 ,  H05K1/18 ,  H01L21/56 ,  H01L25/18 ,  H01L25/00

CPC classification number: H05K1/111 ,  H01L21/56 ,  H01L23/3121 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2924/13055 ,  H01L2924/181 ,  H05K1/0256 ,  H05K1/144 ,  H05K1/181 ,  H05K3/28 ,  H05K3/284 ,  H05K7/1432 ,  H05K2201/0104 ,  H05K2201/042 ,  H05K2201/10303 ,  H05K2201/10318 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.

Abstract translation: 印刷电路板（PCB）具有布置在其顶侧的第一结构化金属化和在垂直方向上布置在第一金属化下方的至少一个第二金属化，平行于第一金属化并与其绝缘。 在PCB顶侧也是裸露的半导体芯片，其具有通过接合线连接到PCB顶面上的第一金属化的相应接触焊盘的接触电极。 在操作期间，接触电极和对应的接触垫的第一部分承载高电压。 所有高电压接触焊盘通过电镀通孔导电连接到第二金属化。 绝缘层完全覆盖芯片周围的芯片和PCB的界定区域，并且所有高压承载接触焊盘和电镀通孔完全被绝缘层覆盖。 在操作期间，接触电极和对应的接触焊盘的第二部分处于低电压。

公开(公告)号：US11322451B2

公开(公告)日：2022-05-03

申请号：US16249172

申请日：2019-01-16

Applicant: Infineon Technologies AG

Inventor： Olaf Hohlfeld ,  Juergen Hoegerl ,  Gottfried Beer ,  Magdalena Hoier ,  Georg Meyer-Berg

IPC: H01L23/538 ,  H01L21/48 ,  H01L23/00 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/373 ,  H01L23/498

Abstract: A power semiconductor module includes a power semiconductor die attached to the first metallized side, a passive component attached to the first metallized side, a first isolation layer encapsulating the power semiconductor die and the passive component, a first structured metallization layer on the first isolation layer, and a first plurality of electrically conductive vias extending through the first isolation layer from the first structured metallization layer to the power semiconductor die and the passive component.