公开(公告)号：US20140151789A1

公开(公告)日：2014-06-05

申请号：US13690328

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。

公开(公告)号：US20250107115A1

公开(公告)日：2025-03-27

申请号：US18826506

申请日：2024-09-06

Applicant: Infineon Technologies AG

Inventor： Manfred Pfaffenlehner ,  Arnab Biswas ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Philipp Seng

IPC: H01L29/861 ,  H01L27/06

Abstract: A power semiconductor diode includes: a semiconductor body with a drift region of a first conductivity type; a first load terminal at a first side of the semiconductor body coupled to an anode region of a second conductivity type in the semiconductor body and coupled to the drift region; a second load terminal at a second side of the semiconductor body coupled to both cathode regions of the first conductivity type and short regions of the second conductivity type of a doped region in the semiconductor body and coupled to the drift region; and a resistive element external of the semiconductor body. The diode conducts a load current between the load terminals, a first path of which crosses the anode region, drift region and cathode regions and a second path of which crosses the anode region, drift region and short regions. The resistive element exhibits a resistance having a positive-temperature-coefficient.

公开(公告)号：US11410989B2

公开(公告)日：2022-08-09

申请号：US16844674

申请日：2020-04-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Roman Baburske ,  Thomas Basler ,  Philip Christoph Brandt ,  Maria Cotorogea

IPC: H01L29/861 ,  H01L29/10 ,  H01L29/06 ,  H01L29/423 ,  H01L29/739 ,  H01L27/02 ,  H01L29/40 ,  H03K17/082 ,  H01L29/08

Abstract: A semiconductor device is operable a forward current mode and a reverse current mode and comprises a semiconductor region, and a controllable charge carrier injector, and a gate. A method includes detecting, in the reverse current mode, if the present load current in the reversed direction does not exceed a threshold value, providing a gate signal such that the gate electrode causes the charge carrier injector to induce a first charge carrier density within the semiconductor region so as to conduct a nominal load current in the reverse direction; if the present load current in the reverse direction does exceed the threshold value, operating the semiconductor device in an overload state by providing the gate signal with a voltage that causes the semiconductor region to conduct an overload current in the reverse direction, wherein the second charge carrier density is higher than the first charge carrier density.

公开(公告)号：US11309410B2

公开(公告)日：2022-04-19

申请号：US16890822

申请日：2020-06-02

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/40 ,  H01L29/08 ,  H01L27/115 ,  H01L27/105 ,  H01L27/11521

Abstract: A semiconductor device is described in which a conductive channel is present along an active gate trench of the device when a gate potential is at an on-voltage, whereas no conductive channel is present along an inactive trench of the device for the same gate potential condition.

公开(公告)号：US20180366541A1

公开(公告)日：2018-12-20

申请号：US16110508

申请日：2018-08-23

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/22 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417 ,  H01L29/40 ,  H01L29/10 ,  H01L29/08 ,  H01L21/311 ,  H01L21/265 ,  H01L21/223

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

公开(公告)号：US20180033705A1

公开(公告)日：2018-02-01

申请号：US15657735

申请日：2017-07-24

Applicant: Infineon Technologies AG

Inventor： Alexander Philippou ,  Erich Griebl ,  Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L21/66 ,  G01R31/02 ,  G01R31/26 ,  H01L23/522 ,  H01L21/8234

Abstract: A semiconductor device includes a first source wiring substructure connected to a plurality of source doping region portions of a transistor structure, and a second source wiring substructure connected to a plurality of source field electrodes located in a plurality of source field trenches extending into a semiconductor substrate. A contact wiring portion of the first source wiring substructure and a contact wiring portion of the second source wiring substructure are located in a wiring layer of a layer stack located on the semiconductor substrate. The contact wiring portion of the first source wiring substructure and the contact wiring portion of the second source wiring substructure each have a lateral size sufficient for a contact for at least a temporary test measurement. The wiring layer including the contact wiring portions is located closer to the substrate than any ohmic electrical connection between the first and the second source wiring substructures.

公开(公告)号：US20170250271A1

公开(公告)日：2017-08-31

申请号：US15594269

申请日：2017-05-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/739 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

公开(公告)号：US09666663B2

公开(公告)日：2017-05-30

申请号：US13963312

申请日：2013-08-09

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea ,  Hans-Joachim Schulze ,  Haybat Itani ,  Erich Griebl ,  Andreas Haghofer

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/22 ,  H01L21/265 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66

CPC classification number: H01L29/06 ,  H01L21/22 ,  H01L21/2236 ,  H01L21/265 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/31111 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7813

Abstract: First and second cell trench structures extend from a first surface into a semiconductor substrate. The first cell trench structure includes a first buried electrode and a first insulator layer between the first buried electrode and a semiconductor mesa separating the first and second cell trench structures. A capping layer covers the first surface. The capping layer is patterned to form an opening having a minimum width larger than a thickness of the first insulator layer. The opening exposes a first vertical section of the first insulator layer at the first surface. An exposed portion of the first insulator layer is removed to form a recess between the semiconductor mesa and the first buried electrode. A contact structure is in the opening and the recess. The contact structure electrically connects both a buried zone in the semiconductor mesa and the first buried electrode and allows for narrower semiconductor mesa width.

公开(公告)号：US20160300945A1

公开(公告)日：2016-10-13

申请号：US15188217

申请日：2016-06-21

Applicant: Infineon Technologies AG

Inventor： Johannes Georg Laven ,  Maria Cotorogea

IPC: H01L29/78 ,  H01L21/265 ,  H01L29/417 ,  H01L29/10 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7813 ,  H01L21/26586 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66719 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/7811

Abstract: A semiconductor device includes first and second cell trench structures extending from a first surface into a semiconductor body, a first semiconductor mesa separating the cell trench structures. The first cell trench structure includes a first buried electrode and a first insulator layer. A first vertical section of the first insulator layer separates the first buried electrode from the first semiconductor mesa. The first semiconductor mesa includes a source zone of a first conductivity type directly adjoining the first surface. The semiconductor device further includes a capping layer on the first surface and a contact structure having a first section in an opening of the capping layer and a second section in the first semiconductor mesa or between the first semiconductor mesa and the first buried electrode. A lateral net impurity concentration of the source zone parallel to the first surface increases in the direction of the contact structure.

Abstract translation: 半导体器件包括从第一表面延伸到半导体本体的第一和第二单元沟道结构，分隔单元沟槽结构的第一半导体台面。 第一单元沟道结构包括第一掩埋电极和第一绝缘体层。 第一绝缘体层的第一垂直部分将第一掩埋电极与第一半导体台面分开。 第一半导体台面包括直接邻接第一表面的第一导电类型的源极区。 所述半导体器件还包括在所述第一表面上的覆盖层，以及接触结构，其具有所述覆盖层的开口中的第一部分和所述第一半导体台面中的第二部分或所述第一半导体台面和所述第一掩埋电极之间的第二部分。 平行于第一表面的源极区域的侧向净杂质浓度在接触结构的方向上增加。

公开(公告)号：US20150349116A1

公开(公告)日：2015-12-03

申请号：US14824388

申请日：2015-08-12

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Frank Wolter ,  Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Yvonne Gawlina-Schmidl

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7397 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/0623 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/7395 ,  H01L29/7813

Abstract: A semiconductor substrate having a first main surface and a transistor cell includes a drift region, a body region between the drift region and the first main surface, an active trench at the first main surface extending into the drift region, a gate insulating layer at sidewalls and a bottom side of the active trench, a gate conductive layer in the active trench, a source region in the body region, and adjacent to the active trench, a body trench at the first main surface extending into the drift region, the body trench being adjacent to the body region and to the drift region, an insulating layer at sidewalls and at a bottom side of the body trench, the insulating layer being asymmetric with respect to an axis extending perpendicular to the first main surface at a center of the body trench, and a conductive layer in the body trench.

Abstract translation: 具有第一主表面和晶体管单元的半导体衬底包括漂移区，漂移区和第一主表面之间的体区，在延伸到漂移区的第一主表面处的有源沟槽，在侧壁处的栅极绝缘层 所述有源沟槽的底侧，所述有源沟槽中的栅极导电层，所述主体区域中的源极区域，并且与所述有源沟槽相邻，所述第一主表面延伸到所述漂移区域中的主体沟槽，所述主体沟槽 邻近身体区域和漂移区域，在体沟槽的侧壁和底侧具有绝缘层，绝缘层相对于在身体的中心处垂直于第一主表面延伸的轴线是不对称的 沟槽，以及导体层。