公开(公告)号：US20150206983A1

公开(公告)日：2015-07-23

申请号：US14162311

申请日：2014-01-23

Applicant: Infineon Technologies AG

Inventor： Hans Peter Felsl ,  Elmar Falck ,  Manfred Pfaffenlehner ,  Frank Hille ,  Andreas Haertl ,  Holger Schulze ,  Daniel Schloegl

IPC: H01L29/861 ,  H01L29/66

CPC classification number: H01L29/0603 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/8611

Abstract: A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.

Abstract translation: 半导体二极管包括具有相反的第一和第二侧面的半导体本体。 第一和第二半导体区域沿着第二侧的横向连续地布置。 第一和第二半导体区域具有相反的第一和第二导电类型，并且在第二侧电耦合到电极。 半导体二极管还包括第二导电类型的第三半导体区域，该第二半导体区域埋在半导体本体中距离第二侧一定距离。 第二和第三半导体区域彼此分离。

公开(公告)号：US20140151789A1

公开(公告)日：2014-06-05

申请号：US13690328

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。

公开(公告)号：US11018252B2

公开(公告)日：2021-05-25

申请号：US16578990

申请日：2019-09-23

Applicant: Infineon Technologies AG

Inventor： Hans Peter Felsl ,  Moriz Jelinek ,  Volodymyr Komarnitskyy ,  Konrad Schraml ,  Hans-Joachim Schulze

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739

Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

公开(公告)号：US09385181B2

公开(公告)日：2016-07-05

申请号：US14162311

申请日：2014-01-23

Applicant: Infineon Technologies AG

Inventor： Hans Peter Felsl ,  Elmar Falck ,  Manfred Pfaffenlehner ,  Frank Hille ,  Andreas Haertl ,  Holger Schulze ,  Daniel Schloegl

IPC: H01L29/861 ,  H01L29/06 ,  H01L29/66 ,  H01L29/36 ,  H01L29/16 ,  H01L29/20

CPC classification number: H01L29/0603 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66128 ,  H01L29/8611

Abstract: A semiconductor diode includes a semiconductor body having opposite first and second sides. A first and a second semiconductor region are consecutively arranged along a lateral direction at the second side. The first and second semiconductor regions are of opposite first and second conductivity types and are electrically coupled to an electrode at the second side. The semiconductor diode further includes a third semiconductor region of the second conductivity type buried in the semiconductor body at a distance from the second side. The second and third semiconductor regions are separated from each other.

Abstract translation: 半导体二极管包括具有相反的第一和第二侧面的半导体本体。 第一和第二半导体区域沿着第二侧的横向连续地布置。 第一和第二半导体区域具有相反的第一和第二导电类型，并且在第二侧电耦合到电极。 半导体二极管还包括第二导电类型的第三半导体区域，该第二半导体区域埋在半导体本体中距离第二侧一定距离。 第二和第三半导体区域彼此分离。

公开(公告)号：US20140370693A1

公开(公告)日：2014-12-18

申请号：US14470996

申请日：2014-08-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz Hirler ,  Hans Peter Felsl ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L29/66 ,  H01L21/302 ,  H01L29/36

CPC classification number: H01L21/02576 ,  H01L21/302 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.

Abstract translation: 一种制造半导体器件的方法包括：通过形成漂移区来形成半导体二极管，在漂移区中或漂移区上形成第一导电类型的第一半导体区域，并通过第一表面的第一表面电耦合第一半导体区域到第一端子 半导体本体，将沟槽蚀刻到半导体本体中，以及在沟槽中形成第二导电类型的沟道区，并且经由半导体本体的第一表面将沟道区电耦合到第一端。 沟道区的第一侧邻接第一半导体区。

公开(公告)号：US08853774B2

公开(公告)日：2014-10-07

申请号：US13690328

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。

公开(公告)号：US20200098911A1

公开(公告)日：2020-03-26

申请号：US16578990

申请日：2019-09-23

Applicant: Infineon Technologies AG

Inventor： Hans Peter Felsl ,  Moriz Jelinek ,  Volodymyr Komarnitskyy ,  Konrad Schraml ,  Hans-Joachim Schulze

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/739

Abstract: A power semiconductor transistor includes a semiconductor body having a front side and a backside with a backside surface. The semiconductor body includes a drift region of a first conductivity type and a field stop region of the first conductivity type. The field stop region is arranged between the drift region and the backside and includes, in a cross-section along a vertical direction from the backside to the front side, a concentration profile of donors of the first conductivity type that has: a first local maximum at a first distance from the backside surface, a front width at half maximum associated with the first local maximum, and a back width at half maximum associated with the first local maximum. The front width at half maximum is smaller than the back width at half maximum and amounts to at least 8% of the first distance.

公开(公告)号：US09293524B2

公开(公告)日：2016-03-22

申请号：US14268033

申请日：2014-05-02

Applicant: Infineon Technologies AG

Inventor： Elmar Falck ,  Wolfgang Roesener ,  Hans Peter Felsl ,  Andre Stegner

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/778 ,  H01L29/74 ,  H01L29/739 ,  H01L21/761

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.

Abstract translation: 半导体器件具有底部和顶侧以及侧面的半导体本体。 在半导体本体中形成有源半导体区域，并且边缘区域围绕有源半导体区域。 第一导电类型的第一半导体区形成在边缘区域中。 在边缘区域中形成具有至少N个场限制结构的边缘终止结构。 每个场限制结构具有形成在半导体本体中的场环和分离沟槽，其中N至少为1.每个场环具有第二导电类型，与第一半导体区形成pn结并且围绕 有源半导体区域。 对于每个场限制结构，该场限制结构的分离沟槽被布置在该场限制结构的场环和有源半导体区之间。

公开(公告)号：US20150318347A1

公开(公告)日：2015-11-05

申请号：US14268033

申请日：2014-05-02

Applicant: Infineon Technologies AG

Inventor： Elmar Falck ,  Wolfgang Roesner ,  Hans Peter Felsl ,  Andre Stegner

IPC: H01L29/06 ,  H01L21/761 ,  H01L29/74 ,  H01L29/739 ,  H01L29/78 ,  H01L29/778

CPC classification number: H01L29/0623 ,  H01L21/761 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/1608 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/22 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/778 ,  H01L29/78 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/8611

Abstract: A semiconductor device has a semiconductor body with bottom and top sides and a lateral surface. An active semiconductor region is formed in the semiconductor body and an edge region surrounds the active semiconductor region. A first semiconductor zone of a first conduction type is formed in the edge region. An edge termination structure having at least N field limiting structures is formed in the edge region. Each of the field limiting structures has a field ring and a separation trench formed in the semiconductor body, where N is at least 1. Each of the field rings has a second conduction type, forms a pn-junction with the first semiconductor zone and surrounds the active semiconductor region. For each of the field limiting structures, the separation trench of that field limiting structure is arranged between the field ring of that field limiting structure and the active semiconductor region.

Abstract translation: 半导体器件具有底部和顶侧以及侧面的半导体本体。 在半导体本体中形成有源半导体区域，并且边缘区域围绕有源半导体区域。 第一导电类型的第一半导体区形成在边缘区域中。 在边缘区域中形成具有至少N个场限制结构的边缘终止结构。 每个场限制结构具有形成在半导体本体中的场环和分离沟槽，其中N至少为1.每个场环具有第二导电类型，与第一半导体区形成pn结并且围绕 有源半导体区域。 对于每个场限制结构，该场限制结构的分离沟槽被布置在该场限制结构的场环和有源半导体区之间。

公开(公告)号：US09048095B2

公开(公告)日：2015-06-02

申请号：US14470996

申请日：2014-08-28

Applicant: Infineon Technologies AG

Inventor： Anton Mauder ,  Franz Hirler ,  Hans Peter Felsl ,  Hans-Joachim Schulze

IPC: H01L21/02 ,  H01L21/302 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/10 ,  H01L29/36 ,  H01L29/423 ,  H01L29/06

CPC classification number: H01L21/02576 ,  H01L21/302 ,  H01L29/0626 ,  H01L29/0692 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/4236 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/7803 ,  H01L29/7813 ,  H01L29/861

Abstract: A method of manufacturing a semiconductor device includes forming a semiconductor diode by forming a drift region, forming a first semiconductor region of a first conductivity type in or on the drift region and electrically coupling the first semiconductor region to a first terminal via a first surface of a semiconductor body, etching a trench into the semiconductor body, and forming a channel region of a second conductivity type in the trench and electrically coupling the channel region to the first terminal via the first surface of the semiconductor body. A first side of the channel region adjoins the first semiconductor region.

Abstract translation: 一种制造半导体器件的方法包括：通过形成漂移区来形成半导体二极管，在漂移区中或漂移区上形成第一导电类型的第一半导体区域，并通过第一表面的第一表面电耦合第一半导体区域到第一端子 半导体本体，将沟槽蚀刻到半导体本体中，以及在沟槽中形成第二导电类型的沟道区，并且经由半导体本体的第一表面将沟道区电耦合到第一端。 沟道区的第一侧邻接第一半导体区。