公开(公告)号：US20240213343A1

公开(公告)日：2024-06-27

申请号：US18533872

申请日：2023-12-08

Applicant: Infineon Technologies AG

Inventor： Roland Dietmüller ,  Andreas Korzenietz ,  Bernd Bitnar ,  Wolfgang Wagner ,  Philip Christoph Brandt ,  Frank Hille ,  Volodymyr Komarnitskyy ,  Frank Pfirsch ,  Franz Josef Niedernostheide ,  Marc Probst

IPC: H01L29/423 ,  H01L29/40 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78

CPC classification number: H01L29/42364 ,  H01L29/401 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A power semiconductor device includes a first region in an active region of a semiconductor body and including first trenches each having a first trench electrode electrically connected to a gate terminal and a first trench insulator. A second region includes second trenches each having a second trench electrode electrically connected to the gate terminal and a second trench insulator. At least one of the following applies: a minimal thickness of each second trench insulator amounts to at least 120% of a corresponding minimal thickness of each first trench insulator; an average thickness of the second trench insulators amounts to at least 120% of an average thickness of the first trench insulators; a trench bottom thickness of each second trench insulator amounts to at least 120% of a corresponding trench bottom thickness of each first trench insulator; a minimal breakdown voltage of each second trench insulator amounts to at least 120% of a minimal breakdown voltage of each first trench insulator.

公开(公告)号：US10756035B2

公开(公告)日：2020-08-25

申请号：US15285250

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Wolfgang Wagner

IPC: H01L23/00

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

公开(公告)号：US20160365413A1

公开(公告)日：2016-12-15

申请号：US15182720

申请日：2016-06-15

Applicant: Infineon Technologies AG

Inventor： Wolfgang Wagner ,  Johannes Baumgartl ,  Volodymyr Komarnitskyy

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/861 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739

CPC classification number: H01L29/1095 ,  H01L29/0834 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

Abstract: A method of producing a semiconductor device includes providing a semiconductor body having a front side 10-1 and a back side, wherein the semiconductor body includes a drift region having dopants of a first conductivity type and a body region having dopants of a second conductivity type complementary to the first conductivity type, a transition between the drift region and the body region forming a pn-junction. The method further comprises: creating a contact groove in the semiconductor body, the contact groove extending into the body region along a vertical direction pointing from the front side to the back side; and filling the contact groove at least partially by epitaxially growing a semiconductor material within the contact groove, wherein the semiconductor material has dopants of the second conductivity type.

Abstract translation: 一种制造半导体器件的方法包括提供具有正面10-1和背面的半导体本体，其中半导体本体包括具有第一导电类型的掺杂剂的漂移区域和具有第二导电类型的掺杂剂的体区域 与第一导电类型互补，漂移区域和形成pn结的体区之间的转变。 该方法还包括：在半导体本体中形成接触槽，该接触槽沿着从前侧指向背侧的垂直方向延伸到本体区域; 以及至少部分地通过在所述接触槽内外延生长半导体材料来填充所述接触槽，其中所述半导体材料具有所述第二导电类型的掺杂剂。

公开(公告)号：US09013027B2

公开(公告)日：2015-04-21

申请号：US13950783

申请日：2013-07-25

Applicant: Infineon Technologies AG

Inventor： Holger Huesken ,  Francisco Javier Santos Rodriguez ,  Wolfgang Wagner

IPC: H01L21/00 ,  H01L23/00 ,  H01L21/762

CPC classification number: H01L23/562 ,  H01L21/76202 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

Abstract translation: 实施例涉及半导体器件，半导体晶片结构以及用于制造或形成半导体晶片结构的方法。 半导体器件包括具有第一导电类型的第一区域和具有第二导电类型的第二区域的半导体衬底。 该半导体器件还包括具有中断区域的氧化物结构和至少在氧化物的中断区域处与第二区域接触的金属层结构。

公开(公告)号：US20140151789A1

公开(公告)日：2014-06-05

申请号：US13690328

申请日：2012-11-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L27/088 ,  H01L21/8234

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。

公开(公告)号：US20170098620A1

公开(公告)日：2017-04-06

申请号：US15285250

申请日：2016-10-04

Applicant: Infineon Technologies AG

Inventor： Roman Roth ,  Wolfgang Wagner

IPC: H01L23/00

CPC classification number: H01L24/05 ,  H01L24/03 ,  H01L24/45 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03622 ,  H01L2224/04042 ,  H01L2224/05118 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/0516 ,  H01L2224/05164 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/05618 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/0566 ,  H01L2224/05664 ,  H01L2224/4502 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00014

Abstract: A semiconductor device is presented. The semiconductor device comprises a semiconductor body coupled to a first load terminal and to a second load terminal and configured to carry a load current between the first load terminal and the second load terminal. The first load terminal comprises a contiguous metal layer coupled to the semiconductor body; and at least one metal island arranged on top of and in contact with the contiguous metal layer and configured to be contacted by an end of a bond wire and to receive at least a part of the load current by means of the bond wire, wherein the contiguous metal layer and the metal island are composed of the same metal.

公开(公告)号：US20150028456A1

公开(公告)日：2015-01-29

申请号：US13950783

申请日：2013-07-25

Applicant: Infineon Technologies AG

Inventor： Holger Huesken ,  Francisco Javier Santos Rodriguez ,  Wolfgang Wagner

IPC: H01L23/00 ,  H01L21/762

CPC classification number: H01L23/562 ,  H01L21/76202 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments relate to a semiconductor device, a semiconductor wafer structure, and a method for manufacturing or forming a semiconductor wafer structure. The semiconductor device includes a semiconductor substrate with a first region having a first conductivity type and a second region having a second conductivity type. The semiconductor device further includes an oxide structure with interrupted areas and a metal layer structure being in contact with the second region at least at the interrupted areas of the oxide.

Abstract translation: 实施例涉及半导体器件，半导体晶片结构以及用于制造或形成半导体晶片结构的方法。 半导体器件包括具有第一导电类型的第一区域和具有第二导电类型的第二区域的半导体衬底。 该半导体器件还包括具有中断区域的氧化物结构和至少在氧化物的中断区域处与第二区域接触的金属层结构。

公开(公告)号：US09899377B2

公开(公告)日：2018-02-20

申请号：US15299645

申请日：2016-10-21

Applicant: Infineon Technologies AG

Inventor： Hans-Joachim Schulze ,  Franz-Josef Niedernostheide ,  Frank Dieter Pfirsch ,  Francisco Javier Santos Rodriguez ,  Stephan Voss ,  Wolfgang Wagner

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/082 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/739 ,  H01L29/66 ,  H01L29/749 ,  H01L29/08 ,  H01L27/06

CPC classification number: H01L27/088 ,  H01L21/823418 ,  H01L21/82345 ,  H01L21/823475 ,  H01L27/0629 ,  H01L27/082 ,  H01L29/0607 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/4983 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/66363 ,  H01L29/7393 ,  H01L29/7396 ,  H01L29/7397 ,  H01L29/749

Abstract: A semiconductor device and a method for producing thereof is provided. The semiconductor device includes a plurality of device cells, each comprising a body region, a source region, and a gate electrode adjacent to the body region and dielectrically insulated from the body region by a gate dielectric; and an electrically conductive gate layer comprising the gate electrodes or electrically connected to the gate electrodes of the plurality of device cells. The gate layer is electrically connected to a gate conductor and includes at least one of an increased resistance region and a decreased resistance region.

公开(公告)号：US09859378B2

公开(公告)日：2018-01-02

申请号：US15182720

申请日：2016-06-15

Applicant: Infineon Technologies AG

Inventor： Wolfgang Wagner ,  Johannes Baumgartl ,  Volodymyr Komarnitskyy

IPC: H01L29/10 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L29/78 ,  H01L29/861 ,  H01L29/417 ,  H01L29/08

CPC classification number: H01L29/1095 ,  H01L29/0834 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813 ,  H01L29/861 ,  H01L29/8613

Abstract: A method of producing a semiconductor device includes providing a semiconductor body having a front side 10-1 and a back side, wherein the semiconductor body includes a drift region having dopants of a first conductivity type and a body region having dopants of a second conductivity type complementary to the first conductivity type, a transition between the drift region and the body region forming a pn-junction. The method further comprises: creating a contact groove in the semiconductor body, the contact groove extending into the body region along a vertical direction pointing from the front side to the back side; and filling the contact groove at least partially by epitaxially growing a semiconductor material within the contact groove, wherein the semiconductor material has dopants of the second conductivity type.

公开(公告)号：US08853774B2

公开(公告)日：2014-10-07

申请号：US13690328

申请日：2012-11-30

Applicant: Infineon Technologies AG

Inventor： Maria Cotorogea ,  Hans Peter Felsl ,  Yvonne Gawlina ,  Francisco Javier Santos Rodriguez ,  Hans-Joachim Schulze ,  Georg Seibert ,  Andre Rainer Stegner ,  Wolfgang Wagner

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088

CPC classification number: H01L27/088 ,  H01L21/823481 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66734 ,  H01L29/7813

Abstract: A semiconductor device includes a first transistor cell including a first gate electrode in a first trench. The semiconductor device further includes a second transistor cell including a second gate electrode in a second trench, wherein the first and second gate electrodes are electrically connected. The semiconductor device further includes a third trench between the first and second trenches, wherein the third trench extends deeper into a semiconductor body from a first side of the semiconductor body than the first and second trenches. The semiconductor device further includes a dielectric in the third trench covering a bottom side and walls of the third trench.

Abstract translation: 半导体器件包括在第一沟槽中包括第一栅电极的第一晶体管单元。 半导体器件还包括在第二沟槽中包括第二栅电极的第二晶体管单元，其中第一和第二栅极电连接。 半导体器件还包括在第一和第二沟槽之间的第三沟槽，其中第三沟槽从半导体本体的第一侧比第一和第二沟槽更深地延伸到半导体本体中。 半导体器件还包括覆盖第三沟槽的底侧和第三沟槽壁的第三沟槽中的电介质。