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    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS
    21.
    发明公开
    TECHNOLOGIES FOR LOW-LEAKAGE ON-CHIP CAPACITORS 审中-公开

    公开(公告)号：US20230317773A1

    公开(公告)日：2023-10-05

    申请号：US17711736

    申请日：2022-04-01

    Applicant: Intel Corporation

    Inventor： Sameer Shekhar ,  Amit K. Jain ,  Chin Lee Kuan

    IPC: H01L49/02 ,  H03H1/00

    CPC classification number: H01L28/92 ,  H03H1/0007 ,  H03H2001/0014

    Abstract: Technologies for low-leakage and low series resistance on-chip capacitors are disclosed. In the illustrative embodiment, each electrode of a capacitor is formed from two metal layers and vias between the metal layers. A high-k dielectric layer is between the metal layers. The electrodes are displaced relative to each other on the plane defined by the high-k dielectric layer. As a result, electric field lines of the capacitor are parallel to the high-k dielectric layer. The electrodes can be displaced from each other by more than the thickness of the high-k dielectric layer, reducing the leakage current through the high-k dielectric layer as compared to a capacitor with field lines perpendicular to the high-k dielectric layer. Such a capacitor may be used to provide power to circuits in a low-power state with little leakage current and/or may be used to absorb radiofrequency (RF) interference.

    Stepped interposer for stacked chip package
    23.
    发明授权
    Stepped interposer for stacked chip package 有权

    公开(公告)号：US11527479B2

    公开(公告)日：2022-12-13

    申请号：US17089744

    申请日：2020-11-05

    Applicant: Intel Corporation

    Inventor： Chin Lee Kuan ,  Bok Eng Cheah ,  Jackson Chung Peng Kong

    IPC: H01L23/538 ,  H01L25/065 ,  H01L21/768 ,  H01L23/64 ,  H01L21/56 ,  H01L23/50

    Abstract: A chip package including a chip; a substrate; an interposer module including a first layer having a larger surface area than the surface area of a second layer, wherein a bottom of the second layer is attached to a top of the first layer area creating an exposed surface area of the first layer; via openings extending at least partially through the first layer; via openings extending at least partially through the first layer and the second layer; a plurality of conductive routing electrically coupled between the via openings, wherein the chip is electrically coupled to the via openings of a top of the second layer, wherein the substrate is electrically coupled to via openings of a bottom of the first layer; and an electronic component electrically coupled to the via openings of the exposed surface area of the first layer.

    Magnetic sensing scheme for voltage regulator circuit
    24.
    发明授权
    Magnetic sensing scheme for voltage regulator circuit 有权

    公开(公告)号：US11502603B2

    公开(公告)日：2022-11-15

    申请号：US16452322

    申请日：2019-06-25

    Applicant: Intel Corporation

    Inventor： Amit Kumar Jain ,  Chin Lee Kuan ,  Sameer Shekhar

    IPC: H02M3/158 ,  H01F27/28 ,  G01R19/165 ,  G06F1/26 ,  H01F27/40 ,  G01R33/028 ,  H02M3/156 ,  H02M1/00

    Abstract: Various embodiments provide a magnetic sensing scheme for a voltage regulator circuit. The voltage regulator circuit may include a first inductor (also referred to as an output inductor) coupled between a drive circuit and an output node. The voltage regulator circuit may further include a second inductor (also referred to as a sense inductor) having a first terminal coupled to the first inductor at a tap point between terminals of the first inductor. The second inductor may provide a sense voltage at a second terminal of the second inductor. A control circuit may control a state of the voltage regulator circuit based on the sense voltage to provide a regulated output voltage at the output node. Other embodiments may be described and claimed.

    PACKAGE EDGE MOUNTED FRAME STRUCTURES
    25.
    发明申请
    PACKAGE EDGE MOUNTED FRAME STRUCTURES 审中-公开

    公开(公告)号：US20200098674A1

    公开(公告)日：2020-03-26

    申请号：US16142249

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Chin Lee Kuan ,  Amit Kumar Jain ,  Sameer Shekhar

    IPC: H01L23/498 ,  H01L25/065 ,  H01L23/00 ,  H01L21/48

    Abstract: Embodiments may relate to a semiconductor package. A conductive frame may be coupled with the semiconductor package. The conductive frame may include a first portion, a second portion, and a third portion positioned between the first portion and the second portion. The first portion may be coupled with the first side of the semiconductor package. The second portion may be coupled with the second side of the semiconductor package. The third portion may be coupled with the sidewall of the semiconductor package. Other embodiments may be described or claimed.

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