公开(公告)号：US11775047B2

公开(公告)日：2023-10-03

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： Jianfang Zhu ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/32 ,  G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

CPC classification number: G06F1/329 ,  G06F1/3228 ,  G06F9/3836 ,  G06F9/4812 ,  G06F9/4893

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US20220374066A1

公开(公告)日：2022-11-24

申请号：US17879256

申请日：2022-08-02

Applicant: INTEL CORPORATION

Inventor： JIANFANG ZHU ,  Deepak Samuel Kirubakaran ,  Raoul Rivas Toledano ,  Chee Lim Nge ,  Rajshree Chabukswar ,  James Hermerding, II ,  Sudheer Nair ,  William Braun ,  Zhongsheng Wang ,  Russell Fenger ,  Udayan Kapaley

IPC: G06F1/329 ,  G06F1/3228 ,  G06F9/38 ,  G06F9/48

Abstract: In one embodiment, a processor includes: at least one core; and a power controller coupled to the at least one core. The power controller may include: a workload monitor circuit to calculate a background task ratio based on a first amount of time that the at least one core executed background tasks during an active duration; and a control circuit to dynamically apply a power management policy for a background mode when the background task ratio exceeds a background mode threshold, the power management policy for the background mode to reduce power consumption of the processor. Other embodiments are described and claimed.

公开(公告)号：US11422849B2

公开(公告)日：2022-08-23

申请号：US16547767

申请日：2019-08-22

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  Vijay Dhanraj ,  Russell Jerome Fenger ,  Hisham Abu-Salah ,  Eliezer Weissmann

IPC: G06F1/32 ,  G06F9/46 ,  G06F9/455 ,  G06F9/48 ,  G06F1/3296 ,  G06F9/50 ,  G06F1/3234 ,  G06F9/38 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F11/34

Abstract: A data processing system with technology for dynamically grouping threads includes a machine-readable medium and first and second cores, each with multiple logical processors (LPs). The system also comprises an operating system which, when executed, enables the system to select an LP to receive a new low-priority thread and to assign the new low-priority thread to the selected LP. The operation of selecting an LP to receive the new low-priority thread comprises, when the first core has multiple idle LPs, automatically determining whether the second core has an idle LP and a busy LP that is executing a current low-priority thread. In response to determining that the second core has an idle LP and a busy LP that is executing a current low-priority thread, the system automatically selects the idle LP in the second core to receive the new low-priority thread. Other embodiments are described and claimed.

公开(公告)号：US11354213B2

公开(公告)日：2022-06-07

申请号：US16647563

申请日：2018-08-27

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F9/46 ,  G06F11/34 ,  G06F11/30 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.

公开(公告)号：US20220114136A1

公开(公告)日：2022-04-14

申请号：US17558172

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Jianfang Zhu ,  Ivan Chen ,  Barnes Cooper ,  Jianwei Dai ,  Martin Dixon ,  Kristoffer Fleming ,  Mark Gallina ,  Duncan Glendinning ,  Deepak Samuel Kirubakaran ,  Chia-Hung S. Kuo ,  Yifan Li ,  Adam Norman ,  Michael Rosenzweig ,  Kai P Wang ,  Jin Yan ,  Virendra Vikramsinh Adsure

IPC: G06F15/78 ,  G06F9/445

Abstract: Methods, systems, and apparatus to reconfigure a computer are disclosed. An example electronic device includes at least one memory, instructions in the electronic device, and processor circuitry to execute instructions to analyze data corresponding to a first configuration of the electronic device to detect a change associated with the electronic device, the first configuration corresponding to a respective first user profile, determine a second configuration of the electronic device based on the detected change, and adjust a configuration of the electronic device from the first configuration to the second configuration.

公开(公告)号：US20210294641A1

公开(公告)日：2021-09-23

申请号：US17342476

申请日：2021-06-08

Applicant: Intel Corporation

Inventor： Deepak Samuel Kirubakaran ,  William A. Braun ,  Rajshree A. Chabukswar ,  Leigh Davies ,  Russell J. Fenger ,  Alexander Gendler ,  Raoul V. Rivas Toledano ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F11/30 ,  G06F11/34

Abstract: Dynamic interrupt steering remaps the handling of interrupts away from processor units executing important workloads. During the operation of a computing system, important workload utilization rates for processor units handling interrupts are determined and those processor units with utilization rates about a threshold value are made unavailable for handling interrupts. Interrupts are dynamically remapped to processor units available for interrupt handling based on processor unit idle state and, in the case of heterogeneous computing systems, processor unit type. Processor units are capable of idle state demotion by, in response to receiving a request to enter into a deep idle state, determining if its interrupt handling rate is greater than a threshold value, and if so, placing itself into a shallower idle state than requested. This avoids the computing system from incurring the expensive idle state exit latency and power costs associated with exiting from a deep idle state.

公开(公告)号：US20210109585A1

公开(公告)日：2021-04-15

申请号：US17129465

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Kristoffer Fleming ,  Melanie Daniels ,  Paul Diefenbaugh ,  Aleksander Magi ,  Lawrence Falkenstein ,  Raoul Rivas Toledano ,  Vishal Sinha ,  Deepak Samuel Kirubakaran ,  Venkateshan Udhayan ,  Marko Bartscherer ,  Kathy Bui

IPC: G06F1/3231 ,  H04W52/02 ,  G06K9/00 ,  H04N5/232 ,  G10L15/18 ,  G10L15/22 ,  G10L15/30 ,  G06F1/3234 ,  G06N20/00

Abstract: Methods and apparatus to improve user experience on computing devices are disclosed. An example computing device includes an image sensor. The example computing device further includes wireless communication circuitry. The example computing device also includes an operations controller to cause the wireless communication circuitry to switch between different operation modes based on an analysis of image data generated by the image sensor. Different ones of the operation modes to consume different amounts of power.

公开(公告)号：US20190102274A1

公开(公告)日：2019-04-04

申请号：US15720585

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Arthur Leonard Brown ,  Russell J. Fenger ,  Deepak Samuel Kirubakaran ,  Asit K. Mallick ,  Jacob Jun Pan ,  Srinivas Pandruvada ,  Efraim Rotem ,  Arjan Van De Ven ,  Eliezer Weissmann ,  Rafal J. Wysocki

IPC: G06F11/34 ,  G06F9/48 ,  G06F9/50

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to: maintain a first utilization metric for a first processing engine; detect a thread transfer from a first processing engine to a second processing engine; and generate, using the first utilization metric for the first processing engine, a second utilization metric for a second processing engine. Other embodiments are described and claimed.