公开(公告)号：US20190123109A1

公开(公告)日：2019-04-25

申请号：US16225130

申请日：2018-12-19

Applicant: Intel Corporation

Inventor： Boping Xie ,  Ansheng Liu ,  Olufemi Isiade Dosunmu ,  Alexander Krichevsky ,  Kelly Christopher Magruder ,  Harel Frish

IPC: H01L27/30 ,  G02B6/42 ,  G02B27/09 ,  G02B7/04 ,  H05K1/02

Abstract: Optical receiver packages and device assemblies that include photodetector (PD) chips having focus lenses monolithically integrated on PD die backsides are disclosed. An example receiver package includes a support structure, a PD die, and an optical input device. The PD die includes a PD, integrated proximate to a first face of the PD die, and further includes a lens, integrated on, or proximate to, an opposite second face. The first face of the PD die faces the support structure, while the second face (“backside”) faces the optical input device. The optical receiver architectures described herein may provide an improvement for the optical alignment tolerance issues, especially for high-speed operation in which the active aperture of the PD may have to be very small. Furthermore, architectures described herein advantageously enable integrating a focus lens in a PD die that may be coupled to the support structure in a flip-chip arrangement.

公开(公告)号：US09709734B2

公开(公告)日：2017-07-18

申请号：US15085766

申请日：2016-03-30

Applicant: Intel Corporation

Inventor： Mahesh Krishnamurthi ,  Judson Ryckman ,  Haisheng Rong ,  Ling Liao ,  Harel Frish ,  Oshrit Harel ,  Assia Barkai ,  Yun-Chung Na ,  Han-Din Liu

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  G02B6/132 ,  G02B6/136

CPC classification number: G02B6/122 ,  G02B6/12002 ,  G02B6/1228 ,  G02B6/132 ,  G02B6/136 ,  G02B6/4214 ,  G02B6/4296 ,  G02B2006/12061 ,  G02B2006/121 ,  G02B2006/12104 ,  G02B2006/12147 ,  G02B2006/12152

Abstract: Embodiments of the present disclosure are directed toward techniques and configurations for an optical coupler. In some embodiments, the device may include an optical waveguide to transmit light input from a light source. The optical waveguide may include a semiconductor layer, having a trench with one facet that comprises an edge formed under an approximately 45 degree angle and another facet formed substantially normal to the semiconductor layer. The edge may interface with another medium to form a mirror to receive inputted light and reflect received light substantially perpendicularly to propagate the received light. Other embodiments may be described and/or claimed.

公开(公告)号：US20250110301A1

公开(公告)日：2025-04-03

申请号：US18477836

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Saeed Fathololoumi ,  Reece Andrew DeFrees ,  Kelly Christopher Magruder ,  Harel Frish ,  John M. Heck ,  Ling Liao ,  David Chak Wang Hui ,  Sushrutha Reddy Gujjula

IPC: G02B6/42 ,  H01L23/00 ,  H01L23/367 ,  H01L25/16 ,  H01L25/18

Abstract: Technologies for thermal plugs in photonic integrated circuit (PIC) dies are disclosed. In an illustrative embodiment, several thermal plugs extend from contact pads in a PIC die, through a dielectric layer, to a waveguide layer. The thermal plugs can carry heat at a higher rate than the surrounding dielectric layer, increasing the heat transfer through the PIC die. The PIC die may be mounted on an electronic integrated circuit (EIC) die in an integrated circuit component. The PIC die can transfer heat from the EIC die, through the PIC die, and to another component such as an integrated heat spreader, lowering the temperature of the EIC die. The thermal plugs can increase the heat transfer through the PIC die.

公开(公告)号：US20250102745A1

公开(公告)日：2025-03-27

申请号：US18475907

申请日：2023-09-27

Applicant: Intel Corporation

Inventor： Mohanraj Prabhugoud ,  David Shia ,  Hari Mahalingam ,  John M. Heck ,  John Robert Macdonald ,  Duncan Peter Dore ,  Eric J. M. Moret ,  Nicholas D. Psaila ,  Sang Yup Kim ,  Shane Kevin Yerkes ,  Harel Frish

IPC: G02B6/42

Abstract: In one embodiment, a device includes a fiber array unit (FAU) coupled to a photonics integrated circuit (PIC) die. The PIC die includes a cavity defined at an edge of the PIC die, with outer edges of the cavity being formed at an angle less than 90 degrees with respect to a bottom surface of the cavity. The PIC die further includes first waveguides protruding into the cavity of the PIC die. The FAU includes a shelf portion extending from a body portion, and a plurality of second waveguides protruding from an outer edge of the shelf portion opposite the body portion. The FAU further includes alignment structures on outer edges of the shelf portion that are in contact with the angled edges of the cavity of the PIC die.

公开(公告)号：US12216158B2

公开(公告)日：2025-02-04

申请号：US17102891

申请日：2020-11-24

Applicant: Intel Corporation

Inventor： Jeremy Hicks ,  Hari Mahalingam ,  Christopher Seibert ,  Eric Snow ,  Harel Frish

IPC: G01R31/311 ,  G02B6/30 ,  G02B6/42

Abstract: Systems and methods for testing a photonic IC (PIC) with an optical probe having an out-of-plane edge coupler to convey test signals between the out-of-plane probe and an edge coupled photonic waveguide within a plane of the PIC. To accommodate dimensions of the optical probe, a test trench may be fabricated in the PIC near an edge coupler of the waveguide. The optical probe may be displaced along one or more axes relative to a prober to position a free end of the prober within the test trench and to align the probe's out-of-plane edge coupler with an edge coupler of a PIC waveguide. Accordingly, a PIC may be probed at the wafer-level, without first dicing a wafer into PIC chips or bars. The optical probe may be physically coupled to a prober through a contact sensor to detect and/or avoid physical contact between probe and PIC.

公开(公告)号：US12057386B2

公开(公告)日：2024-08-06

申请号：US17024507

申请日：2020-09-17

Applicant: Intel Corporation

Inventor： Wei Qian ,  Cung Tran ,  Sungbong Park ,  John Heck ,  Mark Isenberger ,  Seth Slavin ,  Mengyuan Huang ,  Kelly Magruder ,  Harel Frish ,  Reece Defrees ,  Zhi Li

IPC: H01L23/522 ,  H01L23/528

CPC classification number: H01L23/5223 ,  H01L23/528

Abstract: Embedded three-dimensional electrode capacitors, and methods of fabricating three-dimensional electrode capacitors, are described. In an example, an integrated circuit structure includes a first metallization layer above a substrate, the first metallization layer having a first conductive structure in a first dielectric layer, the first conductive structure having a honeycomb pattern. An insulator structure is on the first conductive structure of the first metallization layer. A second metallization layer is above the first metallization layer, the second metallization layer having a second conductive structure in a second dielectric layer, the second conductive structure on the insulator structure, and the second conductive structure having the honeycomb pattern.

公开(公告)号：US20230204877A1

公开(公告)日：2023-06-29

申请号：US17561694

申请日：2021-12-23

Applicant: Intel Corporation

Inventor： John M. Heck ,  Haisheng Rong ,  Harel Frish ,  Ankur Agrawal ,  Boping Xie ,  Randal S. Appleton ,  Hari Mahalingam ,  Alexander Krichevsky ,  Pooya Tadayon ,  Ling Liao ,  Eric J. M. Moret

IPC: G02B6/42

CPC classification number: G02B6/4207 ,  G02B6/4214 ,  G02B6/428

Abstract: Technologies for beam expansion and collimation for photonic integrated circuits (PICs) are disclosed. In one embodiment, an ancillary die is bonded to a PIC die. Vertical couplers in the PIC die direct light from waveguides to flat mirrors on a top side of the ancillary die. The flat mirrors reflect the light towards curved mirrors defined in the bottom surface of the ancillary die. The curved mirrors collimate the light from the waveguides. In another embodiment, a cavity is formed in a PIC die, and curved mirrors are formed in the cavity. Light beams from waveguides in the PIC die are directed to the curved mirrors, which collimate the light beams.

公开(公告)号：US20220122842A1

公开(公告)日：2022-04-21

申请号：US17563968

申请日：2021-12-28

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L21/8234 ,  H01L21/8222

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US20210375620A1

公开(公告)日：2021-12-02

申请号：US16890937

申请日：2020-06-02

Applicant: Intel Corporation

Inventor： Khaled Ahmed ,  Anup Pancholi ,  John Heck ,  Thomas Sounart ,  Harel Frish ,  Sansaptak Dasgupta

IPC: H01L21/02 ,  H01L21/8222 ,  H01L21/8234

Abstract: A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.

公开(公告)号：US11175451B2

公开(公告)日：2021-11-16

申请号：US16733167

申请日：2020-01-02

Applicant: Intel Corporation

Inventor： Hasitha Jayatilleka ,  Harel Frish ,  Ranjeet Kumar ,  Haisheng Rong ,  John Heck

IPC: G02B6/12 ,  G02B6/122 ,  G02B6/134

Abstract: Embodiments include apparatuses, methods, and systems including a semiconductor photonic device having a waveguide disposed above a substrate. The waveguide has a first section including amorphous silicon with a first refractive index, and a second section including crystalline silicon with a second refractive index different from the first refractive index. The semiconductor photonic device further includes a heat element at a vicinity of the first section of the waveguide. The heat element is arranged to generate heat to transform the amorphous silicon of the first section of the waveguide to partially or completely crystallized crystalline silicon with a third refractive index. The amorphous silicon in the first section may be formed with silicon lattice defects caused by an element implanted into the first section. Other embodiments may also be described and claimed.