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    PARTIAL WRITE MANAGEMENT IN A MULTI-TILED COMPUTE ENGINE
    21.
    发明申请
    PARTIAL WRITE MANAGEMENT IN A MULTI-TILED COMPUTE ENGINE 有权

    公开(公告)号：US20210056028A1

    公开(公告)日：2021-02-25

    申请号：US17068754

    申请日：2020-10-12

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  James Valerio ,  Ben Ashbaugh ,  Lakshminarayanan Striramassarma

    IPC: G06F12/0811 ,  G06F3/06 ,  G06F9/38 ,  G06F9/54

    Abstract: Embodiments described herein provide a general purpose graphics processor comprising a plurality of tiles, each tile of the plurality of tiles comprising at least one execution unit, a local cache, and a cache control unit, and a high bandwidth memory communicatively coupled to the plurality of tiles, wherein the high bandwidth memory is shared between the plurality of tiles. The cache control unit is to implement a partial write management protocol to receive a partial write operation directed to a cache line in the local cache, the partial write operation comprising write data, write the data associated with the partial write operation to the local cache when the cache line is in a modified state, and forward the write data associated with the partial write operation to the high bandwidth memory when the partial write operation triggers a cache miss or when the cache line is in an exclusive state or a shared state. Other embodiments may be described and claimed.

    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE
    26.
    发明申请
    APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSING ARCHITECTURE 审中-公开

    公开(公告)号：US20180293690A1

    公开(公告)日：2018-10-11

    申请号：US15482685

    申请日：2017-04-07

    Applicant: Intel Corporation

    Inventor： JOYDEEP RAY ,  ABHISHEK R. APPU ,  ALTUG KOKER ,  BALAJI VEMBU

    IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0875

    CPC classification number: G06T1/20 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/0888 ,  G06F2212/1024 ,  G06F2212/302 ,  G06F2212/455 ,  G06F2212/621 ,  G06T1/60

    Abstract: An apparatus and method are described for managing data which is biased towards a processor or a GPU. For example, one embodiment of an apparatus comprises: a processor comprising one or more cores to execute instructions and process data, one or more cache levels, and cache coherence controllers to maintain coherent data in the one or more cache levels; a graphics processing unit (GPU) to execute graphics instructions and process graphics data, wherein the GPU and processor cores are to share a virtual address space for accessing a system memory; a GPU memory coupled to the GPU, the GPU memory addressable through the virtual address space shared by the processor cores and GPU; and bias management circuitry to store an indication, for each of a plurality of blocks of data, whether the data has a processor bias or a GPU bias, wherein if the data has a GPU bias, then the data is to be accessed by the GPU from the GPU memory without necessarily accessing the processor's cache coherence controllers and wherein requests for the data from the processor cores are processed as uncached requests, preventing the data from being cached in the one or more cache levels of the processor.

    INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS
    30.
    发明公开
    INSTRUCTION PREFETCH BASED ON THREAD DISPATCH COMMANDS 审中-公开

    公开(公告)号：US20230401064A1

    公开(公告)日：2023-12-14

    申请号：US18347964

    申请日：2023-07-06

    Applicant: Intel Corporation

    Inventor： JAMES VALERIO ,  VASANTH RANGANATHAN ,  JOYDEEP RAY ,  PRADEEP RAMANI

    IPC: G06F9/38 ,  G06T1/20 ,  G06F13/28

    CPC classification number: G06F9/3802 ,  G06T1/20 ,  G06F13/28

    Abstract: A graphics processing device is provided that includes a set of compute units to execute a workload, a cache coupled with the set of compute units, and circuitry coupled with the cache and the set of compute units. The circuitry is configured to, in response to a cache miss for the read from a first cache, broadcast an event within the graphics processor device to identify data associated with the cache miss, receive the event at a second compute unit in the set of compute units, and prefetch the data identified by the event into a second cache that is local to the second compute unit before an attempt to read the instruction or data by the second thread.

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